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Hexagon: Rename another copy of Register class
For some reason clang is happy with the conflict, but MSVC is not. llvm-svn: 364196
This commit is contained in:
Matt Arsenault
parent
e9d4d77d16
commit
9b09f68667
@ -79,18 +79,21 @@ namespace {
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// A representation of a register as it can appear in a MachineOperand,
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// i.e. a pair register:subregister.
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struct Register {
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// FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in
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// HexagonGenPredicate
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struct RegisterSubReg {
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unsigned Reg, SubReg;
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explicit Register(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
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explicit Register(const MachineOperand &MO)
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explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
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explicit RegisterSubReg(const MachineOperand &MO)
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: Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
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void print(const TargetRegisterInfo *TRI = nullptr) const {
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dbgs() << printReg(Reg, TRI, SubReg);
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}
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bool operator== (const Register &R) const {
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bool operator== (const RegisterSubReg &R) const {
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return (Reg == R.Reg) && (SubReg == R.SubReg);
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}
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};
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@ -300,7 +303,7 @@ namespace {
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using CellMap = MachineConstPropagator::CellMap;
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virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
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CellMap &Outputs) = 0;
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virtual bool evaluate(const Register &R, const LatticeCell &SrcC,
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virtual bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
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LatticeCell &Result) = 0;
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virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
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SetVector<const MachineBasicBlock*> &Targets,
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@ -343,17 +346,17 @@ namespace {
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// Helper functions.
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bool getCell(const Register &R, const CellMap &Inputs, LatticeCell &RC);
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bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
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bool constToInt(const Constant *C, APInt &Val) const;
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bool constToFloat(const Constant *C, APFloat &Val) const;
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const ConstantInt *intToConst(const APInt &Val) const;
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// Compares.
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bool evaluateCMPrr(uint32_t Cmp, const Register &R1, const Register &R2,
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bool evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2,
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const CellMap &Inputs, bool &Result);
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bool evaluateCMPri(uint32_t Cmp, const Register &R1, const APInt &A2,
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bool evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2,
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const CellMap &Inputs, bool &Result);
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bool evaluateCMPrp(uint32_t Cmp, const Register &R1, uint64_t Props2,
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bool evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2,
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const CellMap &Inputs, bool &Result);
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bool evaluateCMPii(uint32_t Cmp, const APInt &A1, const APInt &A2,
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bool &Result);
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@ -362,52 +365,52 @@ namespace {
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bool evaluateCMPpp(uint32_t Cmp, uint32_t Props1, uint32_t Props2,
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bool &Result);
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bool evaluateCOPY(const Register &R1, const CellMap &Inputs,
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bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
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LatticeCell &Result);
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// Logical operations.
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bool evaluateANDrr(const Register &R1, const Register &R2,
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bool evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateANDri(const Register &R1, const APInt &A2,
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bool evaluateANDri(const RegisterSubReg &R1, const APInt &A2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateANDii(const APInt &A1, const APInt &A2, APInt &Result);
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bool evaluateORrr(const Register &R1, const Register &R2,
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bool evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateORri(const Register &R1, const APInt &A2,
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bool evaluateORri(const RegisterSubReg &R1, const APInt &A2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateORii(const APInt &A1, const APInt &A2, APInt &Result);
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bool evaluateXORrr(const Register &R1, const Register &R2,
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bool evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateXORri(const Register &R1, const APInt &A2,
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bool evaluateXORri(const RegisterSubReg &R1, const APInt &A2,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateXORii(const APInt &A1, const APInt &A2, APInt &Result);
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// Extensions.
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bool evaluateZEXTr(const Register &R1, unsigned Width, unsigned Bits,
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bool evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
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APInt &Result);
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bool evaluateSEXTr(const Register &R1, unsigned Width, unsigned Bits,
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bool evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
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APInt &Result);
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// Leading/trailing bits.
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bool evaluateCLBr(const Register &R1, bool Zeros, bool Ones,
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bool evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
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bool evaluateCTBr(const Register &R1, bool Zeros, bool Ones,
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bool evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
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// Bitfield extract.
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bool evaluateEXTRACTr(const Register &R1, unsigned Width, unsigned Bits,
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bool evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits,
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unsigned Offset, bool Signed, const CellMap &Inputs,
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LatticeCell &Result);
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bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset,
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bool Signed, APInt &Result);
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// Vector operations.
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bool evaluateSplatr(const Register &R1, unsigned Bits, unsigned Count,
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bool evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count,
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const CellMap &Inputs, LatticeCell &Result);
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bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count,
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APInt &Result);
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@ -619,7 +622,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
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LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
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const MachineOperand &MD = PN.getOperand(0);
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Register DefR(MD);
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RegisterSubReg DefR(MD);
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assert(TargetRegisterInfo::isVirtualRegister(DefR.Reg));
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bool Changed = false;
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@ -646,7 +649,7 @@ Bottomize:
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continue;
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}
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const MachineOperand &SO = PN.getOperand(i);
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Register UseR(SO);
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RegisterSubReg UseR(SO);
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// If the input is not a virtual register, we don't really know what
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// value it holds.
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if (!TargetRegisterInfo::isVirtualRegister(UseR.Reg))
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@ -689,7 +692,7 @@ void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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Register DefR(MO);
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RegisterSubReg DefR(MO);
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// Only track virtual registers.
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if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
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continue;
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@ -1065,7 +1068,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
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// --------------------------------------------------------------------
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// Machine const evaluator.
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bool MachineConstEvaluator::getCell(const Register &R, const CellMap &Inputs,
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bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
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LatticeCell &RC) {
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if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
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return false;
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@ -1091,8 +1094,8 @@ const ConstantInt *MachineConstEvaluator::intToConst(const APInt &Val) const {
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return ConstantInt::get(CX, Val);
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}
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bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const Register &R1,
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const Register &R2, const CellMap &Inputs, bool &Result) {
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bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1,
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const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) {
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assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
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LatticeCell LS1, LS2;
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if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
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@ -1130,7 +1133,7 @@ bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const Register &R1,
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return IsTrue || IsFalse;
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}
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bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const Register &R1,
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bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1,
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const APInt &A2, const CellMap &Inputs, bool &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS;
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@ -1157,7 +1160,7 @@ bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const Register &R1,
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return IsTrue || IsFalse;
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}
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bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const Register &R1,
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bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1,
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uint64_t Props2, const CellMap &Inputs, bool &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS;
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@ -1350,13 +1353,13 @@ bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
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return false;
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}
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bool MachineConstEvaluator::evaluateCOPY(const Register &R1,
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bool MachineConstEvaluator::evaluateCOPY(const RegisterSubReg &R1,
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const CellMap &Inputs, LatticeCell &Result) {
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return getCell(R1, Inputs, Result);
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}
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bool MachineConstEvaluator::evaluateANDrr(const Register &R1,
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const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
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bool MachineConstEvaluator::evaluateANDrr(const RegisterSubReg &R1,
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const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
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const LatticeCell &L1 = Inputs.get(R2.Reg);
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const LatticeCell &L2 = Inputs.get(R2.Reg);
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@ -1386,7 +1389,7 @@ bool MachineConstEvaluator::evaluateANDrr(const Register &R1,
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return !Result.isBottom();
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}
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bool MachineConstEvaluator::evaluateANDri(const Register &R1,
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bool MachineConstEvaluator::evaluateANDri(const RegisterSubReg &R1,
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const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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if (A2 == -1)
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@ -1422,8 +1425,8 @@ bool MachineConstEvaluator::evaluateANDii(const APInt &A1,
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return true;
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}
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bool MachineConstEvaluator::evaluateORrr(const Register &R1,
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const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
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bool MachineConstEvaluator::evaluateORrr(const RegisterSubReg &R1,
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const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
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const LatticeCell &L1 = Inputs.get(R2.Reg);
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const LatticeCell &L2 = Inputs.get(R2.Reg);
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@ -1453,7 +1456,7 @@ bool MachineConstEvaluator::evaluateORrr(const Register &R1,
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return !Result.isBottom();
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}
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bool MachineConstEvaluator::evaluateORri(const Register &R1,
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bool MachineConstEvaluator::evaluateORri(const RegisterSubReg &R1,
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const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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if (A2 == 0)
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@ -1489,8 +1492,8 @@ bool MachineConstEvaluator::evaluateORii(const APInt &A1,
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return true;
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}
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bool MachineConstEvaluator::evaluateXORrr(const Register &R1,
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const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
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bool MachineConstEvaluator::evaluateXORrr(const RegisterSubReg &R1,
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const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
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LatticeCell LS1, LS2;
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if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
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@ -1518,7 +1521,7 @@ bool MachineConstEvaluator::evaluateXORrr(const Register &R1,
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return !Result.isBottom();
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}
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bool MachineConstEvaluator::evaluateXORri(const Register &R1,
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bool MachineConstEvaluator::evaluateXORri(const RegisterSubReg &R1,
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const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS1;
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@ -1551,7 +1554,7 @@ bool MachineConstEvaluator::evaluateXORii(const APInt &A1,
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return true;
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}
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bool MachineConstEvaluator::evaluateZEXTr(const Register &R1, unsigned Width,
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bool MachineConstEvaluator::evaluateZEXTr(const RegisterSubReg &R1, unsigned Width,
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unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS1;
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@ -1582,7 +1585,7 @@ bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width,
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return true;
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}
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bool MachineConstEvaluator::evaluateSEXTr(const Register &R1, unsigned Width,
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bool MachineConstEvaluator::evaluateSEXTr(const RegisterSubReg &R1, unsigned Width,
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unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS1;
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@ -1647,7 +1650,7 @@ bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width,
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return true;
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}
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bool MachineConstEvaluator::evaluateCLBr(const Register &R1, bool Zeros,
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bool MachineConstEvaluator::evaluateCLBr(const RegisterSubReg &R1, bool Zeros,
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bool Ones, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS1;
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@ -1682,7 +1685,7 @@ bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros,
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return true;
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}
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bool MachineConstEvaluator::evaluateCTBr(const Register &R1, bool Zeros,
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bool MachineConstEvaluator::evaluateCTBr(const RegisterSubReg &R1, bool Zeros,
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bool Ones, const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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LatticeCell LS1;
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@ -1717,7 +1720,7 @@ bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros,
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return true;
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}
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bool MachineConstEvaluator::evaluateEXTRACTr(const Register &R1,
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bool MachineConstEvaluator::evaluateEXTRACTr(const RegisterSubReg &R1,
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unsigned Width, unsigned Bits, unsigned Offset, bool Signed,
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const CellMap &Inputs, LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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@ -1775,7 +1778,7 @@ bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits,
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return true;
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}
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bool MachineConstEvaluator::evaluateSplatr(const Register &R1,
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bool MachineConstEvaluator::evaluateSplatr(const RegisterSubReg &R1,
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unsigned Bits, unsigned Count, const CellMap &Inputs,
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LatticeCell &Result) {
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assert(Inputs.has(R1.Reg));
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@ -1832,7 +1835,7 @@ namespace {
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bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
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CellMap &Outputs) override;
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bool evaluate(const Register &R, const LatticeCell &SrcC,
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bool evaluate(const RegisterSubReg &R, const LatticeCell &SrcC,
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LatticeCell &Result) override;
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bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
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SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru)
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@ -1847,7 +1850,7 @@ namespace {
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const MachineOperand &MO);
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void replaceWithNop(MachineInstr &MI);
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bool evaluateHexRSEQ32(Register RL, Register RH, const CellMap &Inputs,
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bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
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LatticeCell &Result);
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bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
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CellMap &Outputs);
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@ -1921,14 +1924,14 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
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return false;
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unsigned Opc = MI.getOpcode();
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Register DefR(MD);
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RegisterSubReg DefR(MD);
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assert(!DefR.SubReg);
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if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
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return false;
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if (MI.isCopy()) {
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LatticeCell RC;
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Register SrcR(MI.getOperand(1));
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RegisterSubReg SrcR(MI.getOperand(1));
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bool Eval = evaluateCOPY(SrcR, Inputs, RC);
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if (!Eval)
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return false;
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@ -1950,7 +1953,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
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const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
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const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
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LatticeCell RC;
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Register SrcRL(OpLo), SrcRH(OpHi);
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RegisterSubReg SrcRL(OpLo), SrcRH(OpHi);
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bool Eval = evaluateHexRSEQ32(SrcRL, SrcRH, Inputs, RC);
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if (!Eval)
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return false;
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@ -2037,7 +2040,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
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int64_t B = MI.getOperand(2).getImm();
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assert(B >=0 && B < 32);
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APInt A(32, (1ull << B), false);
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Register R(MI.getOperand(1));
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RegisterSubReg R(MI.getOperand(1));
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LatticeCell RC = Outputs.get(DefR.Reg);
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bool Eval = evaluateORri(R, A, Inputs, RC);
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if (!Eval)
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@ -2077,7 +2080,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
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using namespace Hexagon;
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|
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bool Ones = (Opc == S2_ct1) || (Opc == S2_ct1p);
|
||||
Register R1(MI.getOperand(1));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
assert(Inputs.has(R1.Reg));
|
||||
LatticeCell T;
|
||||
bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T);
|
||||
@ -2109,7 +2112,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
|
||||
|
||||
bool OnlyZeros = (Opc == S2_cl0) || (Opc == S2_cl0p);
|
||||
bool OnlyOnes = (Opc == S2_cl1) || (Opc == S2_cl1p);
|
||||
Register R1(MI.getOperand(1));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
assert(Inputs.has(R1.Reg));
|
||||
LatticeCell T;
|
||||
bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T);
|
||||
@ -2137,7 +2140,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
|
||||
{
|
||||
bool Signed = (Opc == Hexagon::S4_extract) ||
|
||||
(Opc == Hexagon::S4_extractp);
|
||||
Register R1(MI.getOperand(1));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
unsigned BW = getRegBitWidth(R1.Reg);
|
||||
unsigned Bits = MI.getOperand(2).getImm();
|
||||
unsigned Offset = MI.getOperand(3).getImm();
|
||||
@ -2188,7 +2191,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
|
||||
return true;
|
||||
}
|
||||
|
||||
bool HexagonConstEvaluator::evaluate(const Register &R,
|
||||
bool HexagonConstEvaluator::evaluate(const RegisterSubReg &R,
|
||||
const LatticeCell &Input, LatticeCell &Result) {
|
||||
if (!R.SubReg) {
|
||||
Result = Input;
|
||||
@ -2279,7 +2282,7 @@ Undetermined:
|
||||
|
||||
if (SimpleBranch) {
|
||||
const MachineOperand &MD = BrI.getOperand(0);
|
||||
Register PR(MD);
|
||||
RegisterSubReg PR(MD);
|
||||
// If the condition operand has a subregister, this is not something
|
||||
// we currently recognize.
|
||||
if (PR.SubReg)
|
||||
@ -2501,7 +2504,7 @@ void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) {
|
||||
MI.RemoveOperand(0);
|
||||
}
|
||||
|
||||
bool HexagonConstEvaluator::evaluateHexRSEQ32(Register RL, Register RH,
|
||||
bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH,
|
||||
const CellMap &Inputs, LatticeCell &Result) {
|
||||
assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg));
|
||||
LatticeCell LSL, LSH;
|
||||
@ -2570,7 +2573,7 @@ bool HexagonConstEvaluator::evaluateHexCompare(const MachineInstr &MI,
|
||||
if (Computed) {
|
||||
// Only create a zero/non-zero cell. At this time there isn't really
|
||||
// much need for specific values.
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
LatticeCell L = Outputs.get(DefR.Reg);
|
||||
uint32_t P = Result ? ConstantProperties::NonZero
|
||||
: ConstantProperties::Zero;
|
||||
@ -2590,9 +2593,9 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc,
|
||||
bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
|
||||
bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm();
|
||||
if (Reg1) {
|
||||
Register R1(Src1);
|
||||
RegisterSubReg R1(Src1);
|
||||
if (Reg2) {
|
||||
Register R2(Src2);
|
||||
RegisterSubReg R2(Src2);
|
||||
return evaluateCMPrr(Cmp, R1, R2, Inputs, Result);
|
||||
} else if (Imm2) {
|
||||
APInt A2 = getCmpImm(Opc, 2, Src2);
|
||||
@ -2601,7 +2604,7 @@ bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc,
|
||||
} else if (Imm1) {
|
||||
APInt A1 = getCmpImm(Opc, 1, Src1);
|
||||
if (Reg2) {
|
||||
Register R2(Src2);
|
||||
RegisterSubReg R2(Src2);
|
||||
uint32_t NegCmp = Comparison::negate(Cmp);
|
||||
return evaluateCMPri(NegCmp, R2, A1, Inputs, Result);
|
||||
} else if (Imm2) {
|
||||
@ -2620,7 +2623,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
|
||||
return false;
|
||||
const MachineOperand &Src1 = MI.getOperand(1);
|
||||
const MachineOperand &Src2 = MI.getOperand(2);
|
||||
Register R1(Src1);
|
||||
RegisterSubReg R1(Src1);
|
||||
bool Eval = false;
|
||||
LatticeCell RC;
|
||||
switch (Opc) {
|
||||
@ -2628,7 +2631,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
|
||||
return false;
|
||||
case Hexagon::A2_and:
|
||||
case Hexagon::A2_andp:
|
||||
Eval = evaluateANDrr(R1, Register(Src2), Inputs, RC);
|
||||
Eval = evaluateANDrr(R1, RegisterSubReg(Src2), Inputs, RC);
|
||||
break;
|
||||
case Hexagon::A2_andir: {
|
||||
if (!Src2.isImm())
|
||||
@ -2639,7 +2642,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
|
||||
}
|
||||
case Hexagon::A2_or:
|
||||
case Hexagon::A2_orp:
|
||||
Eval = evaluateORrr(R1, Register(Src2), Inputs, RC);
|
||||
Eval = evaluateORrr(R1, RegisterSubReg(Src2), Inputs, RC);
|
||||
break;
|
||||
case Hexagon::A2_orir: {
|
||||
if (!Src2.isImm())
|
||||
@ -2650,11 +2653,11 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
|
||||
}
|
||||
case Hexagon::A2_xor:
|
||||
case Hexagon::A2_xorp:
|
||||
Eval = evaluateXORrr(R1, Register(Src2), Inputs, RC);
|
||||
Eval = evaluateXORrr(R1, RegisterSubReg(Src2), Inputs, RC);
|
||||
break;
|
||||
}
|
||||
if (Eval) {
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
Outputs.update(DefR.Reg, RC);
|
||||
}
|
||||
return Eval;
|
||||
@ -2663,7 +2666,7 @@ bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
|
||||
bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
|
||||
const CellMap &Inputs, CellMap &Outputs) {
|
||||
// Dst0 = Cond1 ? Src2 : Src3
|
||||
Register CR(MI.getOperand(1));
|
||||
RegisterSubReg CR(MI.getOperand(1));
|
||||
assert(Inputs.has(CR.Reg));
|
||||
LatticeCell LS;
|
||||
if (!getCell(CR, Inputs, LS))
|
||||
@ -2678,7 +2681,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
|
||||
return false;
|
||||
|
||||
const MachineOperand &ValOp = MI.getOperand(TakeOp);
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
LatticeCell RC = Outputs.get(DefR.Reg);
|
||||
|
||||
if (ValOp.isImm()) {
|
||||
@ -2691,7 +2694,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
|
||||
return true;
|
||||
}
|
||||
if (ValOp.isReg()) {
|
||||
Register R(ValOp);
|
||||
RegisterSubReg R(ValOp);
|
||||
const LatticeCell &LR = Inputs.get(R.Reg);
|
||||
LatticeCell LSR;
|
||||
if (!evaluate(R, LR, LSR))
|
||||
@ -2706,7 +2709,7 @@ bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
|
||||
bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
|
||||
const CellMap &Inputs, CellMap &Outputs) {
|
||||
// Dst0 = ext R1
|
||||
Register R1(MI.getOperand(1));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
assert(Inputs.has(R1.Reg));
|
||||
|
||||
unsigned Opc = MI.getOpcode();
|
||||
@ -2736,7 +2739,7 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
|
||||
break;
|
||||
}
|
||||
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
unsigned BW = getRegBitWidth(DefR.Reg);
|
||||
LatticeCell RC = Outputs.get(DefR.Reg);
|
||||
bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC)
|
||||
@ -2750,8 +2753,8 @@ bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
|
||||
bool HexagonConstEvaluator::evaluateHexVector1(const MachineInstr &MI,
|
||||
const CellMap &Inputs, CellMap &Outputs) {
|
||||
// DefR = op R1
|
||||
Register DefR(MI.getOperand(0));
|
||||
Register R1(MI.getOperand(1));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
assert(Inputs.has(R1.Reg));
|
||||
LatticeCell RC = Outputs.get(DefR.Reg);
|
||||
bool Eval;
|
||||
@ -2789,7 +2792,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
|
||||
for (const MachineOperand &MO : MI.operands()) {
|
||||
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
|
||||
continue;
|
||||
Register R(MO);
|
||||
RegisterSubReg R(MO);
|
||||
if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
|
||||
continue;
|
||||
HasUse = true;
|
||||
@ -2955,10 +2958,10 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
// to DefR += mpyi(R, #imm),
|
||||
// or DefR -= mpyi(R, #imm).
|
||||
{
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
assert(!DefR.SubReg);
|
||||
Register R2(MI.getOperand(2));
|
||||
Register R3(MI.getOperand(3));
|
||||
RegisterSubReg R2(MI.getOperand(2));
|
||||
RegisterSubReg R3(MI.getOperand(3));
|
||||
assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg));
|
||||
LatticeCell LS2, LS3;
|
||||
// It is enough to get one of the input cells, since we will only try
|
||||
@ -2972,7 +2975,7 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
if (Zero) {
|
||||
// DefR == R1 (tied operands).
|
||||
MachineOperand &Acc = MI.getOperand(1);
|
||||
Register R1(Acc);
|
||||
RegisterSubReg R1(Acc);
|
||||
unsigned NewR = R1.Reg;
|
||||
if (R1.SubReg) {
|
||||
// Generate COPY. FIXME: Replace with the register:subregister.
|
||||
@ -3019,8 +3022,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
|
||||
case Hexagon::A2_and:
|
||||
{
|
||||
Register R1(MI.getOperand(1));
|
||||
Register R2(MI.getOperand(2));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
RegisterSubReg R2(MI.getOperand(2));
|
||||
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
|
||||
LatticeCell LS1, LS2;
|
||||
unsigned CopyOf = 0;
|
||||
@ -3038,8 +3041,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
if (!CopyOf)
|
||||
return false;
|
||||
MachineOperand &SO = MI.getOperand(CopyOf);
|
||||
Register SR(SO);
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg SR(SO);
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
unsigned NewR = SR.Reg;
|
||||
if (SR.SubReg) {
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
|
||||
@ -3055,8 +3058,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
|
||||
case Hexagon::A2_or:
|
||||
{
|
||||
Register R1(MI.getOperand(1));
|
||||
Register R2(MI.getOperand(2));
|
||||
RegisterSubReg R1(MI.getOperand(1));
|
||||
RegisterSubReg R2(MI.getOperand(2));
|
||||
assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg));
|
||||
LatticeCell LS1, LS2;
|
||||
unsigned CopyOf = 0;
|
||||
@ -3070,8 +3073,8 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
|
||||
if (!CopyOf)
|
||||
return false;
|
||||
MachineOperand &SO = MI.getOperand(CopyOf);
|
||||
Register SR(SO);
|
||||
Register DefR(MI.getOperand(0));
|
||||
RegisterSubReg SR(SO);
|
||||
RegisterSubReg DefR(MI.getOperand(0));
|
||||
unsigned NewR = SR.Reg;
|
||||
if (SR.SubReg) {
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user