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GlobalISel: Reimplement widenScalar for G_UNMERGE_VALUES results

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Only use shifts if the requested type exactly matches the source type,
and create sub-unmerges otherwise.
This commit is contained in:
Matt Arsenault 2020-01-21 09:02:42 -05:00
parent c55d376d9d
commit 9b0ab53549
10 changed files with 1541 additions and 1235 deletions
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68
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -1396,7 +1396,7 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
if (TypeIdx != 0)
return UnableToLegalize;
unsigned NumDst = MI.getNumOperands() - 1;
int NumDst = MI.getNumOperands() - 1;
Register SrcReg = MI.getOperand(NumDst).getReg();
LLT SrcTy = MRI.getType(SrcReg);
if (!SrcTy.isScalar())
@ -1407,26 +1407,66 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
if (!DstTy.isScalar())
return UnableToLegalize;
unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
LLT NewSrcTy = LLT::scalar(NewSrcSize);
unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
if (WideTy == SrcTy) {
// Theres no unmerge type to target. Directly extract the bits from the
// source type
unsigned DstSize = DstTy.getSizeInBits();
auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
for (int I = 1; I != NumDst; ++I) {
auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
}
for (unsigned I = 1; I != NumDst; ++I) {
auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
MI.eraseFromParent();
return Legalized;
}
Observer.changingInstr(MI);
// TODO
if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
return UnableToLegalize;
MI.getOperand(NumDst).setReg(WideSrc.getReg(0));
for (unsigned I = 0; I != NumDst; ++I)
widenScalarDst(MI, WideTy, I);
// Extend the source to a wider type.
LLT LCMTy = getLCMType(SrcTy, WideTy);
Observer.changedInstr(MI);
Register WideSrc = SrcReg;
if (LCMTy != SrcTy)
WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
// Create a sequence of unmerges to the original results. since we may have
// widened the source, we will need to pad the results with dead defs to cover
// the source register.
// e.g. widen s16 to s32:
// %1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0:_(s48)
//
// =>
// %4:_(s64) = G_ANYEXT %0:_(s48)
// %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4 ; Requested unmerge
// %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %5 ; unpack to original regs
// %3:_(s16), dead %7 = G_UNMERGE_VALUES %6 ; original reg + extra dead def
const int NumUnmerge = Unmerge->getNumOperands() - 1;
const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
for (int I = 0; I != NumUnmerge; ++I) {
auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
for (int J = 0; J != PartsPerUnmerge; ++J) {
int Idx = I * PartsPerUnmerge + J;
if (Idx < NumDst)
MIB.addDef(MI.getOperand(Idx).getReg());
else {
// Create dead def for excess components.
MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
}
}
MIB.addUse(Unmerge.getReg(I));
}
MI.eraseFromParent();
return Legalized;
}

18
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View File

@ -1029,16 +1029,21 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
};
auto &Builder = getActionDefinitionsBuilder(Op)
// Try to widen to s16 first for small types.
// TODO: Only do this on targets with legal s16 shifts
.minScalarOrEltIf(narrowerThan(LitTyIdx, 16), LitTyIdx, S16)
.widenScalarToNextPow2(LitTyIdx, /*Min*/ 16)
// Clamp the little scalar to s8-s256 and make it a power of 2. It's not
// worth considering the multiples of 64 since 2*192 and 2*384 are not
// valid.
.clampScalar(LitTyIdx, S16, S256)
.widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)
.lowerFor({{S16, V2S16}})
.moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
.fewerElementsIf(all(typeIs(0, S16), vectorWiderThan(1, 32),
elementTypeIs(1, S16)),
changeTo(1, V2S16))
// Clamp the little scalar to s8-s256 and make it a power of 2. It's not
// worth considering the multiples of 64 since 2*192 and 2*384 are not
// valid.
.clampScalar(LitTyIdx, S32, S256)
.widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)
// Break up vectors with weird elements into scalars
.fewerElementsIf(
[=](const LegalityQuery &Query) { return notValidElt(Query, 0); },
@ -1046,8 +1051,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.fewerElementsIf(
[=](const LegalityQuery &Query) { return notValidElt(Query, 1); },
scalarize(1))
.clampScalar(BigTyIdx, S32, S1024)
.lowerFor({{S16, V2S16}});
.clampScalar(BigTyIdx, S32, S1024);
if (Op == G_MERGE_VALUES) {
Builder.widenScalarIf(

43
test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
View File

@ -2,23 +2,42 @@
# RUN: llc -march=aarch64 -O0 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_unmerge_s4
name: test_unmerge_s4_constant
body: |
bb.0:
; CHECK-LABEL: name: test_unmerge_s4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[TRUNC]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s8)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK-LABEL: name: test_unmerge_s4_constant
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: $x0 = COPY [[C1]](s64)
%0:_(s8) = G_CONSTANT i8 0
%1:_(s4), %2:_(s4)= G_UNMERGE_VALUES %0
%3:_(s64) = G_ANYEXT %1
$x0 = COPY %3
...
---
name: test_unmerge_s4
body: |
bb.0:
liveins: $w0
; CHECK-LABEL: name: test_unmerge_s4
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %0
%2:_(s4), %3:_(s4)= G_UNMERGE_VALUES %1
%4:_(s64) = G_ANYEXT %2
%5:_(s64) = G_ANYEXT %3
$x0 = COPY %4
$x1 = COPY %5
...

16
test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
View File

@ -427,14 +427,16 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[UV1]](s32)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[UV2]](s32)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[UV3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ANYEXT]](s64), [[ANYEXT1]](s64), [[ANYEXT2]](s64), [[ANYEXT3]](s64)
; CHECK: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16), [[UV16:%[0-9]+]]:_(s16), [[UV17:%[0-9]+]]:_(s16), [[UV18:%[0-9]+]]:_(s16), [[UV19:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s64>)
; CHECK: S_ENDPGM 0, implicit [[UV4]](s16), implicit [[UV5]](s16), implicit [[UV6]](s16), implicit [[UV7]](s16)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV3]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[TRUNC3]](s16)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<4 x s32>) = G_CONCAT_VECTORS %0, %1

96
test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
View File

@ -545,50 +545,45 @@ body: |
; CHECK-LABEL: name: test_anyext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR2]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[UV]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[UV1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[UV2]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[UV3]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL5]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR5]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[SHL6]]
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT3]], [[SHL7]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C1]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s88)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC3]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_ANYEXT %0
S_ENDPGM 0, implicit %1
@ -616,15 +611,18 @@ body: |
; CHECK-LABEL: name: test_anyext_s2_to_s112
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL1]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)

82
test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
View File

@ -291,31 +291,22 @@ body: |
; CHECK-LABEL: name: test_bitcast_s24_to_v3s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s48)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[TRUNC1]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[SHL]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[COPY1]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[C2]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC2]](s48)
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[TRUNC3]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SHL1]](s64)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s48) = G_TRUNC [[OR1]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC4]](s48)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s96) = G_ANYEXT [[COPY]](s32)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s96)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
@ -332,25 +323,34 @@ body: |
; CHECK-LABEL: name: test_bitcast_s48_to_v3s16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[COPY]](s64)
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC]](s48)
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[UV2]](s16), [[DEF]](s16)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[TRUNC]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[TRUNC1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC2]](s16), [[TRUNC3]](s16)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[DEF1]](s16)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR]](<2 x s16>), [[BUILD_VECTOR1]](<2 x s16>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR2]](<3 x s32>)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0

1215
test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
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143
test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
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@ -615,93 +615,88 @@ body: |
; CHECK-LABEL: name: test_sext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR2]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[UV3]](s16)
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[COPY1]], [[C4]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL3]], [[C4]](s16)
; CHECK: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C3]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[UV]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[UV1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[UV2]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C5]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[UV3]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C5]]
; CHECK: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL5]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[COPY1]], [[C1]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)
; CHECK: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C3]]
; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C5]]
; CHECK: [[SHL6:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C4]](s16)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL6]]
; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C3]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL3]]
; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C5]]
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C3]]
; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C5]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C4]](s16)
; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL7]]
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[SHL8]]
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C1]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[ZEXT3]], [[SHL9]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR7]](s32), [[OR8]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C1]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL4]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL5]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL6]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C5]]
; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C3]]
; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C5]]
; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C4]](s16)
; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL10]]
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C1]](s16)
; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL7]]
; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C5]]
; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C3]]
; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C5]]
; CHECK: [[SHL11:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C4]](s16)
; CHECK: [[OR10:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL11]]
; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C1]](s16)
; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL8]]
; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C5]]
; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C3]]
; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY15]], [[C5]]
; CHECK: [[SHL12:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C4]](s16)
; CHECK: [[OR11:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL12]]
; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY15]], [[C3]]
; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C1]](s16)
; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL9]]
; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY16]], [[C5]]
; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY16]], [[C3]]
; CHECK: [[COPY17:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY17]], [[C5]]
; CHECK: [[SHL13:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C4]](s16)
; CHECK: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL13]]
; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR9]](s16)
; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR10]](s16)
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[ZEXT6]], [[C1]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[ZEXT5]], [[SHL14]]
; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[OR11]](s16)
; CHECK: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[ZEXT8]], [[C1]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[ZEXT7]], [[SHL15]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR13]](s32), [[OR14]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY17]], [[C3]]
; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C1]](s16)
; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL10]]
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR7]](s16)
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL11]]
; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR8]](s16)
; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[OR9]](s16)
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[ZEXT7]], [[C]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL12]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR10]](s32), [[OR11]](s32)
; CHECK: [[MV2:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s88) = G_TRUNC [[MV2]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s88)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s88) = G_TRUNC [[MV2]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_SEXT %0
S_ENDPGM 0, implicit %1

975
test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
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120
test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
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@ -586,49 +586,44 @@ body: |
; CHECK-LABEL: name: test_zext_s32_to_s88
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR2]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[UV]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[UV1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C4]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL3]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[UV2]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[UV3]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C3]]
; CHECK: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL5]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR5]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT2]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT1]], [[SHL6]]
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT4]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT3]], [[SHL7]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64), [[C6]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s88)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C2]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C1]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[OR2]](s16)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[COPY5]](s16)
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR3]](s32), [[OR4]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV1:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64), [[C4]](s64)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s88) = G_TRUNC [[MV1]](s704)
; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s88)
%0:_(s32) = COPY $vgpr0
%1:_(s88) = G_ZEXT %0
S_ENDPGM 0, implicit %1
@ -664,34 +659,37 @@ body: |
; CHECK: [[INSERT:%[0-9]+]]:_(s128) = G_INSERT [[COPY1]], [[C]](s64), 0
; CHECK: [[COPY2:%[0-9]+]]:_(s128) = COPY [[INSERT]](s128)
; CHECK: [[INSERT1:%[0-9]+]]:_(s128) = G_INSERT [[COPY2]], [[TRUNC]](s48), 64
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C3]], [[SHL1]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C4]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV1:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s128) = G_TRUNC [[MV1]](s448)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[TRUNC1]](s128), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s48) = G_EXTRACT [[TRUNC1]](s128), 64
; CHECK: [[COPY3:%[0-9]+]]:_(s128) = COPY [[INSERT1]](s128)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY3]](s128), 0
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s48) = G_EXTRACT [[COPY3]](s128), 64
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[EXTRACT]], [[EXTRACT2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s128) = COPY [[INSERT1]](s128)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY5]](s128), 0
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s48) = G_EXTRACT [[COPY5]](s128), 64
; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[EXTRACT]], [[EXTRACT2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT1]](s48)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT3]](s48)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[AND1]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[AND3]](s64)
; CHECK: [[DEF2:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK: [[COPY4:%[0-9]+]]:_(s128) = COPY [[DEF2]](s128)
; CHECK: [[INSERT2:%[0-9]+]]:_(s128) = G_INSERT [[COPY4]], [[AND]](s64), 0
; CHECK: [[COPY5:%[0-9]+]]:_(s128) = COPY [[INSERT2]](s128)
; CHECK: [[INSERT3:%[0-9]+]]:_(s128) = G_INSERT [[COPY5]], [[TRUNC2]](s48), 64
; CHECK: [[COPY6:%[0-9]+]]:_(s128) = COPY [[DEF2]](s128)
; CHECK: [[INSERT2:%[0-9]+]]:_(s128) = G_INSERT [[COPY6]], [[AND2]](s64), 0
; CHECK: [[COPY7:%[0-9]+]]:_(s128) = COPY [[INSERT2]](s128)
; CHECK: [[INSERT3:%[0-9]+]]:_(s128) = G_INSERT [[COPY7]], [[TRUNC2]](s48), 64
; CHECK: [[TRUNC3:%[0-9]+]]:_(s112) = G_TRUNC [[INSERT3]](s128)
; CHECK: S_ENDPGM 0, implicit [[TRUNC3]](s112)
%0:_(s32) = COPY $vgpr0