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[X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.
llvm-svn: 321632
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@ -1160,6 +1160,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Custom);
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setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v16i1, MVT::v16i32);
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setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v16i1, MVT::v16i32);
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setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
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setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
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setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1, MVT::v4i32);
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setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1, MVT::v4i32);
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if (Subtarget.hasVLX()) {
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i1, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Custom);
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}
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// Extends of v16i1/v8i1 to 128-bit vectors.
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v16i8, Custom);
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@ -16671,9 +16682,29 @@ SDValue X86TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
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MVT VT = Op.getSimpleValueType();
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if (VT.isVector()) {
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assert(Subtarget.hasDQI() && Subtarget.hasVLX() && "Requires AVX512DQVL!");
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SDValue Src = Op.getOperand(0);
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SDLoc dl(Op);
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if (VT == MVT::v2i1 && Src.getSimpleValueType() == MVT::v2f64) {
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MVT ResVT = MVT::v4i32;
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MVT TruncVT = MVT::v4i1;
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unsigned Opc = IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI;
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if (!IsSigned && !Subtarget.hasVLX()) {
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// Widen to 512-bits.
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ResVT = MVT::v8i32;
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TruncVT = MVT::v8i1;
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Opc = ISD::FP_TO_UINT;
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Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8f64,
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DAG.getUNDEF(MVT::v8f64),
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Src, DAG.getIntPtrConstant(0, dl));
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}
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SDValue Res = DAG.getNode(Opc, dl, ResVT, Src);
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Res = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Res);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i1, Res,
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DAG.getIntPtrConstant(0, dl));
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}
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assert(Subtarget.hasDQI() && Subtarget.hasVLX() && "Requires AVX512DQVL!");
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if (VT == MVT::v2i64 && Src.getSimpleValueType() == MVT::v2f32) {
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return DAG.getNode(IsSigned ? X86ISD::CVTTP2SI : X86ISD::CVTTP2UI, dl, VT,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
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