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[X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions llvm-svn: 320275
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@ -934,7 +934,7 @@ multiclass RELEASE_BINOP_MI<SDNode op> {
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[(atomic_store_64 addr:$dst, (op
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[(atomic_store_64 addr:$dst, (op
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(atomic_load_64 addr:$dst), GR64:$src))]>;
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(atomic_load_64 addr:$dst), GR64:$src))]>;
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}
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}
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let Defs = [EFLAGS] in {
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let Defs = [EFLAGS], SchedRW = [WriteMicrocoded] in {
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defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
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defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
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defm RELEASE_AND : RELEASE_BINOP_MI<and>;
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defm RELEASE_AND : RELEASE_BINOP_MI<and>;
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defm RELEASE_OR : RELEASE_BINOP_MI<or>;
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defm RELEASE_OR : RELEASE_BINOP_MI<or>;
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@ -947,7 +947,7 @@ let Defs = [EFLAGS] in {
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// FIXME: imm version.
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// FIXME: imm version.
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// FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
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// FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
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// FIXME: This could also handle SIMD operations with *ps and *pd instructions.
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// FIXME: This could also handle SIMD operations with *ps and *pd instructions.
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let usesCustomInserter = 1 in {
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let usesCustomInserter = 1, SchedRW = [WriteMicrocoded] in {
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multiclass RELEASE_FP_BINOP_MI<SDNode op> {
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multiclass RELEASE_FP_BINOP_MI<SDNode op> {
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def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
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def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
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"#BINOP "#NAME#"32mr PSEUDO!",
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"#BINOP "#NAME#"32mr PSEUDO!",
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@ -981,7 +981,7 @@ multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
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[(atomic_store_64 addr:$dst, dag64)]>;
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[(atomic_store_64 addr:$dst, dag64)]>;
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}
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}
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let Defs = [EFLAGS], Predicates = [UseIncDec] in {
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let Defs = [EFLAGS], Predicates = [UseIncDec], SchedRW = [WriteMicrocoded] in {
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defm RELEASE_INC : RELEASE_UNOP<
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defm RELEASE_INC : RELEASE_UNOP<
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(add (atomic_load_8 addr:$dst), (i8 1)),
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(add (atomic_load_8 addr:$dst), (i8 1)),
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(add (atomic_load_16 addr:$dst), (i16 1)),
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(add (atomic_load_16 addr:$dst), (i16 1)),
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@ -1011,6 +1011,7 @@ defm RELEASE_NOT : RELEASE_UNOP<
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(not (atomic_load_64 addr:$dst))>;
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(not (atomic_load_64 addr:$dst))>;
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*/
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*/
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let SchedRW = [WriteMicrocoded] in {
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def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
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def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
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"#RELEASE_MOV8mi PSEUDO!",
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"#RELEASE_MOV8mi PSEUDO!",
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[(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
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[(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
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@ -1049,6 +1050,7 @@ def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
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def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
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def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
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"#ACQUIRE_MOV64rm PSEUDO!",
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"#ACQUIRE_MOV64rm PSEUDO!",
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[(set GR64:$dst, (atomic_load_64 addr:$src))]>;
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[(set GR64:$dst, (atomic_load_64 addr:$src))]>;
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} // SchedRW
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// DAG Pattern Matching Rules
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// DAG Pattern Matching Rules
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