From 9b52058816142af69ff6aa8a009c9bbdec76e208 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 10 Nov 2016 17:43:52 +0000 Subject: [PATCH] [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes llvm-svn: 286481 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 ++- test/CodeGen/X86/known-bits-vector.ll | 14 ++------------ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 5ad4dcb5b88..15dbacdfb4a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2394,7 +2394,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, unsigned InBits = InVT.getScalarSizeInBits(); KnownZero = KnownZero.zext(InBits); KnownOne = KnownOne.zext(InBits); - computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); + computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, + Depth + 1); KnownZero = KnownZero.trunc(BitWidth); KnownOne = KnownOne.trunc(BitWidth); break; diff --git a/test/CodeGen/X86/known-bits-vector.ll b/test/CodeGen/X86/known-bits-vector.ll index d1b8f03069f..454f428c46c 100644 --- a/test/CodeGen/X86/known-bits-vector.ll +++ b/test/CodeGen/X86/known-bits-vector.ll @@ -190,22 +190,12 @@ define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) n define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind { ; X32-LABEL: knownbits_mask_trunc_shuffle_shl: ; X32: # BB#0: -; X32-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 -; X32-NEXT: vextractf128 $1, %ymm0, %xmm1 -; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] -; X32-NEXT: vpslld $22, %xmm0, %xmm0 -; X32-NEXT: vzeroupper +; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X32-NEXT: retl ; ; X64-LABEL: knownbits_mask_trunc_shuffle_shl: ; X64: # BB#0: -; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 -; X64-NEXT: vextractf128 $1, %ymm0, %xmm1 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] -; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] -; X64-NEXT: vpslld $22, %xmm0, %xmm0 -; X64-NEXT: vzeroupper +; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; X64-NEXT: retq %1 = and <4 x i64> %a0, %2 = trunc <4 x i64> %1 to <4 x i32>