RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

Next powerpc long double bits. Comparisons work,

Browse Source 
although not well, and shortening FP converts.

llvm-svn: 42672
This commit is contained in:
Dale Johannesen 2007-10-06 01:24:11 +00:00
parent b600202c68
commit 9b7ac95116
2 changed files with 60 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -3314,7 +3314,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
MVT::ValueType newVT = Op.getValueType();
MVT::ValueType oldVT = Op.getOperand(0).getValueType();
if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
// The only way we can lower this is to turn it into a STORE,
if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) {
SDOperand Lo, Hi;
ExpandOp(Node->getOperand(0), Lo, Hi);
if (newVT == MVT::f64)
Result = Hi;
else
Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi);
break;
} else {
// The only other way we can lower this is to turn it into a STORE,
// LOAD pair, targetting a temporary location (a stack slot).
// NOTE: there is a choice here between constantly creating new stack
@ -3342,6 +3351,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break;
}
}
}
// FALL THROUGH
case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND:
@ -3995,7 +4005,7 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
SDOperand &RHS,
SDOperand &CC) {
SDOperand Tmp1, Tmp2, Result;
SDOperand Tmp1, Tmp2, Tmp3, Result;
switch (getTypeAction(LHS.getValueType())) {
case Legal:
@ -4127,7 +4137,26 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
ExpandOp(LHS, LHSLo, LHSHi);
ExpandOp(RHS, RHSLo, RHSHi);
switch (cast<CondCodeSDNode>(CC)->get()) {
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
if (VT==MVT::ppcf128) {
// FIXME: This generated code sucks. We want to generate
// FCMP crN, hi1, hi2
// BNE crN, L:
// FCMP crN, lo1, lo2
// The following can be improved, but not that much.
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
Tmp2 = SDOperand();
break;
}
switch (CCCode) {
case ISD::SETEQ:
case ISD::SETNE:
if (RHSLo == RHSHi)
@ -4159,7 +4188,6 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
// FIXME: This generated code sucks.
ISD::CondCode LowCC;
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (CCCode) {
default: assert(0 && "Unknown integer setcc!");
case ISD::SETLT:

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -73,6 +73,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
// Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
setConvertAction(MVT::ppcf128, MVT::f64, Expand);
setConvertAction(MVT::ppcf128, MVT::f32, Expand);
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);