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ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
comparison that would overflow. - The other under/overflow cases can't actually happen because the immediates which would trigger them are legal (so we don't enter this code), but adjusted the style to make it clear the transform is always valid. llvm-svn: 112053
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@ -2271,28 +2271,28 @@ ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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default: break;
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case ISD::SETLT:
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case ISD::SETGE:
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if (isLegalICmpImmediate(C-1)) {
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if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
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CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
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RHS = DAG.getConstant(C-1, MVT::i32);
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}
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break;
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case ISD::SETULT:
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case ISD::SETUGE:
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if (C > 0 && isLegalICmpImmediate(C-1)) {
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if (C != 0 && isLegalICmpImmediate(C-1)) {
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CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
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RHS = DAG.getConstant(C-1, MVT::i32);
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}
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break;
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case ISD::SETLE:
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case ISD::SETGT:
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if (isLegalICmpImmediate(C+1)) {
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if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
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CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
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RHS = DAG.getConstant(C+1, MVT::i32);
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}
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break;
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case ISD::SETULE:
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case ISD::SETUGT:
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if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
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if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
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CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
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RHS = DAG.getConstant(C+1, MVT::i32);
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}
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@ -39,3 +39,17 @@ define i1 @f5(i32 %a) {
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%tmp = icmp eq i32 %a, 1114112
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ret i1 %tmp
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}
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; Check that we don't do an invalid (a > b) --> !(a < b + 1) transform.
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;
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; CHECK: f6:
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; CHECK-NOT: cmp.w r0, #-2147483648
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; CHECK: bx lr
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define i32 @f6(i32 %a) {
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%tmp = icmp sgt i32 %a, 2147483647
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br i1 %tmp, label %true, label %false
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true:
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ret i32 2
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false:
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ret i32 0
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}
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