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[X86] Strengthen type constraints on some specialized X86 ISD opcodes that don't have any flexibility. NFC

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These particular instructions only operate on 128-bit vectors and have no wider equivalents. And the
element size is always known.

One could argue that MOVSS/MOVSD could be merged, but that's probably disruptive to code in
X86ISelLowering and probably low value.

llvm-svn: 360815
This commit is contained in:
Craig Topper 2019-05-15 21:16:28 +00:00
parent b500c0beb0
commit 9be0608242
1 changed files with 16 additions and 4 deletions
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20
lib/Target/X86/X86InstrFragmentsSIMD.td
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@ -365,11 +365,23 @@ def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2OpFP>;
def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2OpFP>;
def X86Movsd : SDNode<"X86ISD::MOVSD",
SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>,
SDTCisVT<1, v2f64>,
SDTCisVT<2, v2f64>]>>;
def X86Movss : SDNode<"X86ISD::MOVSS",
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
SDTCisVT<1, v4f32>,
SDTCisVT<2, v4f32>]>>;
def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2OpFP>;
def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2OpFP>;
def X86Movlhps : SDNode<"X86ISD::MOVLHPS",
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
SDTCisVT<1, v4f32>,
SDTCisVT<2, v4f32>]>>;
def X86Movhlps : SDNode<"X86ISD::MOVHLPS",
SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
SDTCisVT<1, v4f32>,
SDTCisVT<2, v4f32>]>>;
def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
SDTCisVec<1>, SDTCisInt<1>,