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[VE][TTI] don't advertise vregs/vops
Claim to not have any vector support to dissuade SLP, LV and friends from generating SIMD IR for the VE target. We will take this back once vector isel is stable. Reviewed By: kaz7, fhahn Differential Revision: https://reviews.llvm.org/D90462
This commit is contained in:
Simon Moll
parent
4abaee6284
commit
9bff67230d
@ -40,11 +40,28 @@ public:
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
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unsigned getNumberOfRegisters(unsigned ClassID) const {
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bool VectorRegs = (ClassID == 1);
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if (VectorRegs) {
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// TODO report vregs once vector isel is stable.
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return 0;
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}
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unsigned getRegisterBitWidth(bool Vector) const { return 64; }
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return 64;
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}
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unsigned getMinVectorRegisterBitWidth() const { return 64; }
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unsigned getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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// TODO report vregs once vector isel is stable.
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return 0;
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}
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return 64;
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}
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unsigned getMinVectorRegisterBitWidth() const {
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// TODO report vregs once vector isel is stable.
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return 0;
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}
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};
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} // namespace llvm
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38
test/Transforms/LoopVectorize/VE/disable_lv.ll
Normal file
38
test/Transforms/LoopVectorize/VE/disable_lv.ll
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@ -0,0 +1,38 @@
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; RUN: opt < %s -loop-vectorize -mtriple=ve-linux -S | FileCheck %s -check-prefix=VE
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; RUN: opt < %s -loop-vectorize -mtriple=x86_64-pc_linux -mcpu=core-avx2 -S | FileCheck %s -check-prefix=AVX
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; Make sure LV does not trigger for VE on an appealing loop that vectorizes for x86 AVX.
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; TODO: Remove this test once VE vector isel is deemed stable.
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; VE-NOT: llvm.loop.isvectorized
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; AVX: llvm.loop.isvectorized
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define dso_local void @foo(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32 signext %n) local_unnamed_addr {
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %omp.inner.for.body.preheader, label %simd.if.end
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omp.inner.for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %n to i64
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br label %omp.inner.for.body
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omp.inner.for.body: ; preds = %omp.inner.for.body.preheader, %omp.inner.for.body
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%indvars.iv = phi i64 [ 0, %omp.inner.for.body.preheader ], [ %indvars.iv.next, %omp.inner.for.body ]
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%arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4, !llvm.access.group !6
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%mul6 = mul nsw i32 %0, 3
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%arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %mul6, i32* %arrayidx8, align 4, !llvm.access.group !6
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %simd.if.end, label %omp.inner.for.body, !llvm.loop !7
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simd.if.end: ; preds = %omp.inner.for.body, %entry
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ret void
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}
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!6 = distinct !{}
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!7 = distinct !{!7, !8, !9}
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!8 = !{!"llvm.loop.parallel_accesses", !6}
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!9 = !{!"llvm.loop.vectorize.enable", i1 true}
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4
test/Transforms/LoopVectorize/VE/lit.local.cfg
Normal file
4
test/Transforms/LoopVectorize/VE/lit.local.cfg
Normal file
@ -0,0 +1,4 @@
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if not 'X86' in config.root.targets:
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config.unsupported = True
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if not 'VE' in config.root.targets:
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config.unsupported = True
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77
test/Transforms/SLPVectorizer/VE/disable_slp.ll
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77
test/Transforms/SLPVectorizer/VE/disable_slp.ll
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@ -0,0 +1,77 @@
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; RUN: opt < %s -basic-aa -slp-vectorizer -mtriple=ve-linux -S | FileCheck %s -check-prefix=VE
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; RUN: opt < %s -basic-aa -slp-vectorizer -mtriple=x86_64-pc_linux -mcpu=core-avx2 -S | FileCheck %s -check-prefix=SSE
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; Make sure SLP does not trigger for VE on an appealing set of combinable loads
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; and stores that vectorizes for x86 SSE.
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; TODO: Remove this test once VE vector isel is deemed stable.
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; VE-NOT: x double
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; SSE: x double
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define void @foo(double* noalias %A0p, double* noalias %B0p) {
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entry:
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%A1p = getelementptr inbounds double, double* %A0p, i64 1
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%A2p = getelementptr inbounds double, double* %A0p, i64 2
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%A3p = getelementptr inbounds double, double* %A0p, i64 3
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%A4p = getelementptr inbounds double, double* %A0p, i64 4
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%A5p = getelementptr inbounds double, double* %A0p, i64 5
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%A6p = getelementptr inbounds double, double* %A0p, i64 6
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%A7p = getelementptr inbounds double, double* %A0p, i64 7
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%A8p = getelementptr inbounds double, double* %A0p, i64 8
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%A9p = getelementptr inbounds double, double* %A0p, i64 9
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%A10p = getelementptr inbounds double, double* %A0p, i64 10
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%A11p = getelementptr inbounds double, double* %A0p, i64 11
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%A12p = getelementptr inbounds double, double* %A0p, i64 12
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%A13p = getelementptr inbounds double, double* %A0p, i64 13
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%A14p = getelementptr inbounds double, double* %A0p, i64 14
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%A15p = getelementptr inbounds double, double* %A0p, i64 15
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%A0 = load double, double* %A0p, align 8
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%A1 = load double, double* %A1p, align 8
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%A2 = load double, double* %A2p, align 8
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%A3 = load double, double* %A3p, align 8
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%A4 = load double, double* %A4p, align 8
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%A5 = load double, double* %A5p, align 8
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%A6 = load double, double* %A6p, align 8
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%A7 = load double, double* %A7p, align 8
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%A8 = load double, double* %A8p, align 8
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%A9 = load double, double* %A9p, align 8
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%A10 = load double, double* %A10p, align 8
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%A11 = load double, double* %A11p, align 8
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%A12 = load double, double* %A12p, align 8
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%A13 = load double, double* %A13p, align 8
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%A14 = load double, double* %A14p, align 8
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%A15 = load double, double* %A15p, align 8
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%B1p = getelementptr inbounds double, double* %B0p, i64 1
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%B2p = getelementptr inbounds double, double* %B0p, i64 2
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%B3p = getelementptr inbounds double, double* %B0p, i64 3
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%B4p = getelementptr inbounds double, double* %B0p, i64 4
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%B5p = getelementptr inbounds double, double* %B0p, i64 5
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%B6p = getelementptr inbounds double, double* %B0p, i64 6
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%B7p = getelementptr inbounds double, double* %B0p, i64 7
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%B8p = getelementptr inbounds double, double* %B0p, i64 8
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%B9p = getelementptr inbounds double, double* %B0p, i64 9
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%B10p = getelementptr inbounds double, double* %B0p, i64 10
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%B11p = getelementptr inbounds double, double* %B0p, i64 11
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%B12p = getelementptr inbounds double, double* %B0p, i64 12
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%B13p = getelementptr inbounds double, double* %B0p, i64 13
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%B14p = getelementptr inbounds double, double* %B0p, i64 14
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%B15p = getelementptr inbounds double, double* %B0p, i64 15
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store double %A0, double* %B0p, align 8
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store double %A1, double* %B1p, align 8
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store double %A2, double* %B2p, align 8
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store double %A3, double* %B3p, align 8
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store double %A4, double* %B4p, align 8
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store double %A5, double* %B5p, align 8
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store double %A6, double* %B6p, align 8
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store double %A7, double* %B7p, align 8
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store double %A8, double* %B8p, align 8
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store double %A9, double* %B9p, align 8
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store double %A10, double* %B10p, align 8
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store double %A11, double* %B11p, align 8
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store double %A12, double* %B12p, align 8
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store double %A13, double* %B13p, align 8
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store double %A14, double* %B14p, align 8
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store double %A15, double* %B15p, align 8
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ret void
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}
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4
test/Transforms/SLPVectorizer/VE/lit.local.cfg
Normal file
4
test/Transforms/SLPVectorizer/VE/lit.local.cfg
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@ -0,0 +1,4 @@
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if not 'X86' in config.root.targets:
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config.unsupported = True
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if not 'VE' in config.root.targets:
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config.unsupported = True
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