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[Hexagon] Add instruction definitions for Hexagon V66
llvm-svn: 348411
This commit is contained in:
Krzysztof Parzyszek
parent
d531e71318
commit
9c30836a61
@ -358,7 +358,7 @@ def : Proc<"hexagonv65", HexagonModelV65,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
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FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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def : Proc<"hexagonv66", HexagonModelV65, // Use v65, to be fixed soon.
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def : Proc<"hexagonv66", HexagonModelV66,
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[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
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FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
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FeatureNVS, FeaturePackets, FeatureSmallData]>;
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@ -25,11 +25,14 @@ def tc_1ad8a370 : InstrItinClass;
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def tc_1ba8a0cd : InstrItinClass;
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def tc_20a4bbec : InstrItinClass;
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def tc_257f6f7c : InstrItinClass;
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def tc_26a377fe : InstrItinClass;
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def tc_2c745bb8 : InstrItinClass;
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def tc_2d4051cd : InstrItinClass;
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def tc_2e8f5f6e : InstrItinClass;
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def tc_309dbb4f : InstrItinClass;
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def tc_3904b926 : InstrItinClass;
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def tc_3aacf4a8 : InstrItinClass;
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def tc_3ad719fb : InstrItinClass;
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def tc_3c56e5ce : InstrItinClass;
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def tc_3ce09744 : InstrItinClass;
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def tc_3e2aaafc : InstrItinClass;
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@ -45,6 +48,7 @@ def tc_56c4f9fe : InstrItinClass;
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def tc_56e64202 : InstrItinClass;
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def tc_58d21193 : InstrItinClass;
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def tc_5bf8afbb : InstrItinClass;
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def tc_61bf7c03 : InstrItinClass;
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def tc_649072c2 : InstrItinClass;
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def tc_660769f1 : InstrItinClass;
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def tc_663c80a7 : InstrItinClass;
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@ -61,10 +65,12 @@ def tc_8772086c : InstrItinClass;
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def tc_87adc037 : InstrItinClass;
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def tc_8e420e4d : InstrItinClass;
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def tc_90bcc1db : InstrItinClass;
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def tc_933f2b39 : InstrItinClass;
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def tc_946013d8 : InstrItinClass;
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def tc_9d1dc972 : InstrItinClass;
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def tc_9f363d21 : InstrItinClass;
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def tc_a02a10a8 : InstrItinClass;
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def tc_a0dbea28 : InstrItinClass;
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def tc_a7e6707d : InstrItinClass;
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def tc_ab23f776 : InstrItinClass;
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def tc_abe8c3b2 : InstrItinClass;
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@ -82,9 +88,13 @@ def tc_c7039829 : InstrItinClass;
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def tc_cd94bfe0 : InstrItinClass;
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def tc_d8287c14 : InstrItinClass;
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def tc_db5555f3 : InstrItinClass;
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def tc_dd5b0695 : InstrItinClass;
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def tc_df80eeb0 : InstrItinClass;
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def tc_e2d2e9e5 : InstrItinClass;
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def tc_e35c1e93 : InstrItinClass;
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def tc_e3f68a46 : InstrItinClass;
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def tc_e675c45a : InstrItinClass;
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def tc_e699ae41 : InstrItinClass;
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def tc_e8797b98 : InstrItinClass;
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def tc_e99d4c2e : InstrItinClass;
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def tc_f1de44ef : InstrItinClass;
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@ -180,11 +190,21 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
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[HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
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@ -205,6 +225,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
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[HVX_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -287,6 +312,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_XLANE]>], [9, 2],
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[HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
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[HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_649072c2, /*SLOT23,VX*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
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@ -369,6 +399,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_946013d8, /*SLOT0123,VP*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>], [9, 5],
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@ -391,6 +426,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
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[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [3, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -484,6 +524,16 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [2, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -491,6 +541,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
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[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL]>], [3],
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@ -501,6 +556,11 @@ class DepHVXItinV55 {
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InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [1, 2],
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[Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
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[InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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@ -621,11 +681,21 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
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[HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
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@ -646,6 +716,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
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[HVX_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -728,6 +803,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_XLANE]>], [9, 2],
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[HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
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[HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_649072c2, /*SLOT23,VX*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
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@ -810,6 +890,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_946013d8, /*SLOT0123,VP*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>], [9, 5],
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@ -832,6 +917,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
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[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [3, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -925,6 +1015,16 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [2, 1, 2],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
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[InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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@ -932,6 +1032,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
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[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
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InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL]>], [3],
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@ -942,6 +1047,11 @@ class DepHVXItinV60 {
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InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
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[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
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[InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_ZW]>], [1, 2],
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[Hex_FWD, Hex_FWD]>,
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InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
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[InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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@ -1062,11 +1172,21 @@ class DepHVXItinV62 {
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InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
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[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
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[HVX_FWD, HVX_FWD, HVX_FWD]>,
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InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
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[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
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InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
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[InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
|
||||
@ -1087,6 +1207,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1169,6 +1294,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_649072c2, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
|
||||
@ -1251,6 +1381,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_946013d8, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5],
|
||||
@ -1273,6 +1408,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1366,6 +1506,16 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1373,6 +1523,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3],
|
||||
@ -1383,6 +1538,11 @@ class DepHVXItinV62 {
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
@ -1503,11 +1663,21 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
|
||||
@ -1528,6 +1698,11 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1610,6 +1785,11 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_649072c2, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
|
||||
@ -1692,6 +1872,11 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_946013d8, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5],
|
||||
@ -1714,6 +1899,11 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1807,6 +1997,16 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
@ -1814,6 +2014,11 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3],
|
||||
@ -1824,6 +2029,502 @@ class DepHVXItinV65 {
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e99d4c2e, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_f1de44ef, /*SLOT2,VX_DV*/
|
||||
[InstrStage<1, [SLOT2], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_f21e8abb, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_fd7610da, /*SLOT1,LOAD,VA_DV*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>
|
||||
];
|
||||
}
|
||||
|
||||
class DepHVXItinV66 {
|
||||
list<InstrItinData> DepHVXItinV66_list = [
|
||||
InstrItinData <tc_04da405a, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05058f6f, /*SLOT1,LOAD,VA_DV*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05ac6f98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_05ca8cfd, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_08a4f1b6, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_0b04c6c7, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_0ec46cf9, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_131f1c81, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_1381a97c, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [],
|
||||
[]>,
|
||||
|
||||
InstrItinData <tc_15fdf750, /*SLOT23,VS_VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
|
||||
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_16ff9ef8, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_191381c1, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7],
|
||||
[Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_1ad8a370, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_1ba8a0cd, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_20a4bbec, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_257f6f7c, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_26a377fe, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2c745bb8, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_2d4051cd, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_2e8f5f6e, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_309dbb4f, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3904b926, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3aacf4a8, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ad719fb, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3c56e5ce, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3ce09744, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_3e2aaafc, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_447d9895, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_453fe68d, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_46d6c3e0, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_51d0ecc3, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_52447ecc, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_540c3da3, /*SLOT0,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1],
|
||||
[Hex_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_54a0dc47, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_561aaa58, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_56c4f9fe, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_56e64202, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_58d21193, /*SLOT0,STORE,VA_DV*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_5bf8afbb, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_61bf7c03, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_649072c2, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_660769f1, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_663c80a7, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 3, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_6942b6e0, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_6e7fa133, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_71646d06, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7177e272, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_718b5c53, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9],
|
||||
[HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7273323b, /*SLOT0,STORE,VA_DV*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_7417e785, /*SLOT0123,VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_SHIFT]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_767c4e9d, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_7e6a3e89, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_8772086c, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_87adc037, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_8e420e4d, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_90bcc1db, /*SLOT2,VX_DV*/
|
||||
[InstrStage<1, [SLOT2], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_933f2b39, /*SLOT23,4SLOT_MPY*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_946013d8, /*SLOT0123,VP*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 5],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_9d1dc972, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_9f363d21, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a02a10a8, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_a0dbea28, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [3, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_a7e6707d, /*SLOT0,NOSLOT1,LOAD,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_ab23f776, /*SLOT0,STORE*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST]>], [1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_abe8c3b2, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_ac4046bc, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_af25efd9, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7],
|
||||
[HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_b091f1c6, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_b28e51aa, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [2],
|
||||
[Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_b4416217, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7],
|
||||
[HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_b9db8205, /*SLOT01,LOAD*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c0749f3c, /*SLOT01,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2],
|
||||
[HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c127de3a, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_c4edf264, /*SLOT23,VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2],
|
||||
[HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_c5dba46e, /*SLOT0,STORE,VA*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7],
|
||||
[Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_c7039829, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_cd94bfe0, /*SLOT23,VS_VX*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>,
|
||||
InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2],
|
||||
[HVX_FWD, HVX_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_d8287c14, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_db5555f3, /*SLOT0123,VA_DV*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_dd5b0695, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [2, 1, 2],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_df80eeb0, /*SLOT0123,VP_VS*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e2d2e9e5, /*SLOT0,NOSLOT1,STORE,VP*/
|
||||
[InstrStage<1, [SLOT0], 0>,
|
||||
InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ST], 0>,
|
||||
InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5],
|
||||
[Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e35c1e93, /*SLOT0123,VA*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e3f68a46, /*SLOT0123,4SLOT*/
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_ALL]>], [3],
|
||||
[HVX_FWD]>,
|
||||
|
||||
InstrItinData <tc_e675c45a, /*SLOT23,VX_DV*/
|
||||
[InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2],
|
||||
[HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e699ae41, /*SLOT01,ZW*/
|
||||
[InstrStage<1, [SLOT0, SLOT1], 0>,
|
||||
InstrStage<1, [CVI_ZW]>], [1, 2],
|
||||
[Hex_FWD, Hex_FWD]>,
|
||||
|
||||
InstrItinData <tc_e8797b98, /*SLOT1,LOAD,VA*/
|
||||
[InstrStage<1, [SLOT1], 0>,
|
||||
InstrStage<1, [CVI_LD], 0>,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -210,6 +210,14 @@ class Enc_d7dc10 : OpcodeHexagon {
|
||||
bits <2> Pd4;
|
||||
let Inst{1-0} = Pd4{1-0};
|
||||
}
|
||||
class Enc_6baed4 : OpcodeHexagon {
|
||||
bits <3> Ii;
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_736575 : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{21-20} = Ii{10-9};
|
||||
@ -363,6 +371,14 @@ class Enc_ee5ed0 : OpcodeHexagon {
|
||||
bits <2> n1;
|
||||
let Inst{9-8} = n1{1-0};
|
||||
}
|
||||
class Enc_bddee3 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <5> Vyyyy32;
|
||||
let Inst{4-0} = Vyyyy32{4-0};
|
||||
bits <3> Rx8;
|
||||
let Inst{18-16} = Rx8{2-0};
|
||||
}
|
||||
class Enc_935d9b : OpcodeHexagon {
|
||||
bits <5> Ii;
|
||||
let Inst{6-3} = Ii{4-1};
|
||||
@ -502,6 +518,14 @@ class Enc_27fd0e : OpcodeHexagon {
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_d7bc34 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <3> Rt8;
|
||||
let Inst{18-16} = Rt8{2-0};
|
||||
bits <5> Vyyyy32;
|
||||
let Inst{4-0} = Vyyyy32{4-0};
|
||||
}
|
||||
class Enc_93af4c : OpcodeHexagon {
|
||||
bits <7> Ii;
|
||||
let Inst{10-4} = Ii{6-0};
|
||||
@ -667,6 +691,16 @@ class Enc_1b64fb : OpcodeHexagon {
|
||||
bits <5> Rt32;
|
||||
let Inst{12-8} = Rt32{4-0};
|
||||
}
|
||||
class Enc_c1d806 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <5> Vv32;
|
||||
let Inst{20-16} = Vv32{4-0};
|
||||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
bits <2> Qe4;
|
||||
let Inst{6-5} = Qe4{1-0};
|
||||
}
|
||||
class Enc_c6220b : OpcodeHexagon {
|
||||
bits <2> Ii;
|
||||
let Inst{13-13} = Ii{1-1};
|
||||
@ -1060,6 +1094,14 @@ class Enc_b0e9d8 : OpcodeHexagon {
|
||||
bits <5> Rx32;
|
||||
let Inst{4-0} = Rx32{4-0};
|
||||
}
|
||||
class Enc_1bd127 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <3> Rt8;
|
||||
let Inst{18-16} = Rt8{2-0};
|
||||
bits <5> Vdddd32;
|
||||
let Inst{4-0} = Vdddd32{4-0};
|
||||
}
|
||||
class Enc_3694bd : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{21-20} = Ii{10-9};
|
||||
@ -1168,6 +1210,15 @@ class Enc_412ff0 : OpcodeHexagon {
|
||||
bits <5> Rxx32;
|
||||
let Inst{12-8} = Rxx32{4-0};
|
||||
}
|
||||
class Enc_ef601b : OpcodeHexagon {
|
||||
bits <4> Ii;
|
||||
let Inst{13-13} = Ii{3-3};
|
||||
let Inst{10-8} = Ii{2-0};
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
}
|
||||
class Enc_c9a18e : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{21-20} = Ii{10-9};
|
||||
@ -1484,12 +1535,6 @@ class Enc_a198f6 : OpcodeHexagon {
|
||||
bits <5> Rd32;
|
||||
let Inst{4-0} = Rd32{4-0};
|
||||
}
|
||||
class Enc_ed48be : OpcodeHexagon {
|
||||
bits <2> Ii;
|
||||
let Inst{6-5} = Ii{1-0};
|
||||
bits <3> Rdd8;
|
||||
let Inst{2-0} = Rdd8{2-0};
|
||||
}
|
||||
class Enc_4e4a80 : OpcodeHexagon {
|
||||
bits <2> Qs4;
|
||||
let Inst{6-5} = Qs4{1-0};
|
||||
@ -1657,6 +1702,15 @@ class Enc_bd1cbc : OpcodeHexagon {
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_c85e2a : OpcodeHexagon {
|
||||
bits <5> Ii;
|
||||
let Inst{12-8} = Ii{4-0};
|
||||
bits <5> II;
|
||||
let Inst{22-21} = II{4-3};
|
||||
let Inst{7-5} = II{2-0};
|
||||
bits <5> Rd32;
|
||||
let Inst{4-0} = Rd32{4-0};
|
||||
}
|
||||
class Enc_a30110 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
@ -2308,6 +2362,14 @@ class Enc_16c48b : OpcodeHexagon {
|
||||
bits <5> Vw32;
|
||||
let Inst{4-0} = Vw32{4-0};
|
||||
}
|
||||
class Enc_895bd9 : OpcodeHexagon {
|
||||
bits <2> Qu4;
|
||||
let Inst{9-8} = Qu4{1-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vx32;
|
||||
let Inst{4-0} = Vx32{4-0};
|
||||
}
|
||||
class Enc_ea23e4 : OpcodeHexagon {
|
||||
bits <5> Rtt32;
|
||||
let Inst{12-8} = Rtt32{4-0};
|
||||
@ -2844,6 +2906,16 @@ class Enc_e07374 : OpcodeHexagon {
|
||||
bits <5> Rd32;
|
||||
let Inst{4-0} = Rd32{4-0};
|
||||
}
|
||||
class Enc_e0820b : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <5> Vv32;
|
||||
let Inst{20-16} = Vv32{4-0};
|
||||
bits <2> Qs4;
|
||||
let Inst{6-5} = Qs4{1-0};
|
||||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
}
|
||||
class Enc_323f2d : OpcodeHexagon {
|
||||
bits <6> II;
|
||||
let Inst{11-8} = II{5-2};
|
||||
@ -2968,6 +3040,14 @@ class Enc_163a3c : OpcodeHexagon {
|
||||
bits <5> Rt32;
|
||||
let Inst{4-0} = Rt32{4-0};
|
||||
}
|
||||
class Enc_a75aa6 : OpcodeHexagon {
|
||||
bits <5> Rs32;
|
||||
let Inst{20-16} = Rs32{4-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{12-8} = Rt32{4-0};
|
||||
bits <1> Mu2;
|
||||
let Inst{13-13} = Mu2{0-0};
|
||||
}
|
||||
class Enc_b087ac : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
@ -2976,6 +3056,14 @@ class Enc_b087ac : OpcodeHexagon {
|
||||
bits <5> Vd32;
|
||||
let Inst{4-0} = Vd32{4-0};
|
||||
}
|
||||
class Enc_691712 : OpcodeHexagon {
|
||||
bits <2> Pv4;
|
||||
let Inst{12-11} = Pv4{1-0};
|
||||
bits <1> Mu2;
|
||||
let Inst{13-13} = Mu2{0-0};
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_b1e1fb : OpcodeHexagon {
|
||||
bits <11> Ii;
|
||||
let Inst{21-20} = Ii{10-9};
|
||||
@ -3128,16 +3216,11 @@ class Enc_e83554 : OpcodeHexagon {
|
||||
bits <5> Rx32;
|
||||
let Inst{20-16} = Rx32{4-0};
|
||||
}
|
||||
class Enc_eca7c8 : OpcodeHexagon {
|
||||
class Enc_ed48be : OpcodeHexagon {
|
||||
bits <2> Ii;
|
||||
let Inst{13-13} = Ii{1-1};
|
||||
let Inst{7-7} = Ii{0-0};
|
||||
bits <5> Rs32;
|
||||
let Inst{20-16} = Rs32{4-0};
|
||||
bits <5> Ru32;
|
||||
let Inst{12-8} = Ru32{4-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{4-0} = Rt32{4-0};
|
||||
let Inst{6-5} = Ii{1-0};
|
||||
bits <3> Rdd8;
|
||||
let Inst{2-0} = Rdd8{2-0};
|
||||
}
|
||||
class Enc_f8c1c4 : OpcodeHexagon {
|
||||
bits <2> Pv4;
|
||||
@ -3392,13 +3475,24 @@ class Enc_a6ce9c : OpcodeHexagon {
|
||||
bits <4> Rs16;
|
||||
let Inst{7-4} = Rs16{3-0};
|
||||
}
|
||||
class Enc_895bd9 : OpcodeHexagon {
|
||||
bits <2> Qu4;
|
||||
let Inst{9-8} = Qu4{1-0};
|
||||
class Enc_3b7631 : OpcodeHexagon {
|
||||
bits <5> Vu32;
|
||||
let Inst{12-8} = Vu32{4-0};
|
||||
bits <5> Vdddd32;
|
||||
let Inst{4-0} = Vdddd32{4-0};
|
||||
bits <3> Rx8;
|
||||
let Inst{18-16} = Rx8{2-0};
|
||||
}
|
||||
class Enc_eca7c8 : OpcodeHexagon {
|
||||
bits <2> Ii;
|
||||
let Inst{13-13} = Ii{1-1};
|
||||
let Inst{7-7} = Ii{0-0};
|
||||
bits <5> Rs32;
|
||||
let Inst{20-16} = Rs32{4-0};
|
||||
bits <5> Ru32;
|
||||
let Inst{12-8} = Ru32{4-0};
|
||||
bits <5> Rt32;
|
||||
let Inst{20-16} = Rt32{4-0};
|
||||
bits <5> Vx32;
|
||||
let Inst{4-0} = Vx32{4-0};
|
||||
let Inst{4-0} = Rt32{4-0};
|
||||
}
|
||||
class Enc_4b39e4 : OpcodeHexagon {
|
||||
bits <3> Ii;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -251,6 +251,7 @@ def V6_vaslhv_altAlias : InstAlias<"$Vd32 = vaslh($Vu32,$Vv32)", (V6_vaslhv HvxV
|
||||
def V6_vaslw_acc_altAlias : InstAlias<"$Vx32 += vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vaslw_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vaslwv_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vasr_into_altAlias : InstAlias<"$Vxx32 = vasrinto($Vu32,$Vv32)", (V6_vasr_into HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrh_acc_altAlias : InstAlias<"$Vx32 += vasrh($Vu32,$Rt32)", (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrh_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
|
||||
def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>;
|
||||
@ -401,6 +402,7 @@ def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
|
||||
def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
|
||||
def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32 += vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vrmpyubv_altAlias : InstAlias<"$Vd32 = vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vrotr_altAlias : InstAlias<"$Vd32 = vrotr($Vu32,$Vv32)", (V6_vrotr HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vroundhb_altAlias : InstAlias<"$Vd32 = vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vroundhub_altAlias : InstAlias<"$Vd32 = vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
def V6_vrounduhub_altAlias : InstAlias<"$Vd32 = vrounduhub($Vu32,$Vv32):sat", (V6_vrounduhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>;
|
||||
@ -472,4 +474,6 @@ def V6_vunpackub_altAlias : InstAlias<"$Vdd32 = vunpackub($Vu32)", (V6_vunpackub
|
||||
def V6_vunpackuh_altAlias : InstAlias<"$Vdd32 = vunpackuh($Vu32)", (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
|
||||
def V6_vzb_altAlias : InstAlias<"$Vdd32 = vzxtb($Vu32)", (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
|
||||
def V6_vzh_altAlias : InstAlias<"$Vdd32 = vzxth($Vu32)", (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>;
|
||||
def V6_zld0Alias : InstAlias<"z = vmem($Rt32)", (V6_zLd_ai IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
|
||||
def V6_zldp0Alias : InstAlias<"if ($Pv4) z = vmem($Rt32)", (V6_zLd_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
|
||||
def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>;
|
||||
|
||||
@ -24,6 +24,8 @@ inline bool is_TC3x(unsigned SchedClass) {
|
||||
case Hexagon::Sched::tc_13bfbcf9:
|
||||
case Hexagon::Sched::tc_174516e8:
|
||||
case Hexagon::Sched::tc_1a2fd869:
|
||||
case Hexagon::Sched::tc_1c4528a2:
|
||||
case Hexagon::Sched::tc_32779c6f:
|
||||
case Hexagon::Sched::tc_5b54b33f:
|
||||
case Hexagon::Sched::tc_6b25e783:
|
||||
case Hexagon::Sched::tc_76851da1:
|
||||
@ -31,6 +33,7 @@ inline bool is_TC3x(unsigned SchedClass) {
|
||||
case Hexagon::Sched::tc_a9d88b22:
|
||||
case Hexagon::Sched::tc_bafaade3:
|
||||
case Hexagon::Sched::tc_bcf98408:
|
||||
case Hexagon::Sched::tc_bdceeac1:
|
||||
case Hexagon::Sched::tc_c8ce0b5c:
|
||||
case Hexagon::Sched::tc_d1aa9eaa:
|
||||
case Hexagon::Sched::tc_d773585a:
|
||||
@ -53,6 +56,7 @@ inline bool is_TC2early(unsigned SchedClass) {
|
||||
|
||||
inline bool is_TC4x(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_2f7c551d:
|
||||
case Hexagon::Sched::tc_2ff964b4:
|
||||
case Hexagon::Sched::tc_3a867367:
|
||||
case Hexagon::Sched::tc_3b470976:
|
||||
@ -69,7 +73,9 @@ inline bool is_TC2(unsigned SchedClass) {
|
||||
switch (SchedClass) {
|
||||
case Hexagon::Sched::tc_002cb246:
|
||||
case Hexagon::Sched::tc_14b5c689:
|
||||
case Hexagon::Sched::tc_1c80410a:
|
||||
case Hexagon::Sched::tc_4414d8b1:
|
||||
case Hexagon::Sched::tc_6132ba3d:
|
||||
case Hexagon::Sched::tc_61830035:
|
||||
case Hexagon::Sched::tc_679309b8:
|
||||
case Hexagon::Sched::tc_703e822c:
|
||||
@ -81,6 +87,8 @@ inline bool is_TC2(unsigned SchedClass) {
|
||||
case Hexagon::Sched::tc_a813cf9a:
|
||||
case Hexagon::Sched::tc_bfec0f01:
|
||||
case Hexagon::Sched::tc_cf8126ae:
|
||||
case Hexagon::Sched::tc_d08ee0f4:
|
||||
case Hexagon::Sched::tc_e4a7f9f0:
|
||||
case Hexagon::Sched::tc_f429765c:
|
||||
case Hexagon::Sched::tc_f675fee8:
|
||||
case Hexagon::Sched::tc_f9058dd7:
|
||||
@ -100,7 +108,6 @@ inline bool is_TC1(unsigned SchedClass) {
|
||||
case Hexagon::Sched::tc_20cdee80:
|
||||
case Hexagon::Sched::tc_2332b92e:
|
||||
case Hexagon::Sched::tc_2eabeebe:
|
||||
case Hexagon::Sched::tc_3a2ec948:
|
||||
case Hexagon::Sched::tc_3d495a39:
|
||||
case Hexagon::Sched::tc_4c5ba658:
|
||||
case Hexagon::Sched::tc_56336eb0:
|
||||
@ -122,7 +129,6 @@ inline bool is_TC1(unsigned SchedClass) {
|
||||
case Hexagon::Sched::tc_b31c2e97:
|
||||
case Hexagon::Sched::tc_b4b5c03a:
|
||||
case Hexagon::Sched::tc_b51dc29a:
|
||||
case Hexagon::Sched::tc_bf41e621:
|
||||
case Hexagon::Sched::tc_cd374165:
|
||||
case Hexagon::Sched::tc_cfd8378a:
|
||||
case Hexagon::Sched::tc_d5b7b0c1:
|
||||
@ -138,4 +144,4 @@ inline bool is_TC1(unsigned SchedClass) {
|
||||
}
|
||||
} // namespace llvm
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@ -1505,13 +1505,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
|
||||
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
|
||||
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
|
||||
|
||||
// Subtarget-specific operation actions.
|
||||
//
|
||||
if (Subtarget.hasV60Ops()) {
|
||||
setOperationAction(ISD::ROTL, MVT::i32, Custom);
|
||||
setOperationAction(ISD::ROTL, MVT::i64, Custom);
|
||||
}
|
||||
|
||||
// V5+.
|
||||
setOperationAction(ISD::FMA, MVT::f64, Expand);
|
||||
setOperationAction(ISD::FADD, MVT::f64, Expand);
|
||||
@ -1542,6 +1535,17 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
|
||||
setIndexedStoreAction(ISD::POST_INC, VT, Legal);
|
||||
}
|
||||
|
||||
// Subtarget-specific operation actions.
|
||||
//
|
||||
if (Subtarget.hasV60Ops()) {
|
||||
setOperationAction(ISD::ROTL, MVT::i32, Custom);
|
||||
setOperationAction(ISD::ROTL, MVT::i64, Custom);
|
||||
}
|
||||
if (Subtarget.hasV66Ops()) {
|
||||
setOperationAction(ISD::FADD, MVT::f64, Legal);
|
||||
setOperationAction(ISD::FSUB, MVT::f64, Legal);
|
||||
}
|
||||
|
||||
if (Subtarget.useHVXOps())
|
||||
initializeHVXLowering();
|
||||
|
||||
|
||||
@ -1259,12 +1259,19 @@ def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>;
|
||||
def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>;
|
||||
def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>;
|
||||
|
||||
let Predicates = [HasV66] in {
|
||||
def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>;
|
||||
def: OpR_RR_pat<F2_dfsub, pf2<fsub>, f64, F64>;
|
||||
}
|
||||
|
||||
// In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add,
|
||||
// over add-add with individual multiplies as inputs.
|
||||
let AddedComplexity = 10 in {
|
||||
def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>;
|
||||
def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>;
|
||||
def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>;
|
||||
let Predicates = [HasV66] in
|
||||
def: AccRRR_pat<M2_mnaci, Sub, Su<Mul>, I32, I32, I32>;
|
||||
}
|
||||
|
||||
def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>;
|
||||
|
||||
@ -547,11 +547,11 @@ let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
|
||||
addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
||||
def NAME#_pci : STInst<(outs IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_327843a7>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e86aa961>;
|
||||
|
||||
def NAME#_pcr : STInst<(outs IntRegs:$Rx32),
|
||||
(ins IntRegs:$Rx32in, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_c4f596e3>;
|
||||
".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_da97ee82>;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -27,6 +27,7 @@ def CVI_SHIFT : FuncUnit;
|
||||
def CVI_MPY0 : FuncUnit;
|
||||
def CVI_MPY1 : FuncUnit;
|
||||
def CVI_LD : FuncUnit;
|
||||
def CVI_ZW : FuncUnit; // Z register write port
|
||||
|
||||
// Combined functional units.
|
||||
def CVI_XLSHF : FuncUnit;
|
||||
@ -84,3 +85,9 @@ include "HexagonScheduleV62.td"
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV65.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V66 Machine Info +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "HexagonScheduleV66.td"
|
||||
|
||||
@ -65,7 +65,7 @@ def HexagonItinerariesV60 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM],
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>;
|
||||
|
||||
def HexagonModelV60 : SchedMachineModel {
|
||||
|
||||
@ -21,7 +21,7 @@ def HexagonItinerariesV62 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM],
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
|
||||
|
||||
def HexagonModelV62 : SchedMachineModel {
|
||||
|
||||
@ -23,7 +23,7 @@ def HexagonItinerariesV65 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM],
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD],
|
||||
HexagonV65ItinList.ItinList>;
|
||||
|
||||
|
||||
41
lib/Target/Hexagon/HexagonScheduleV66.td
Normal file
41
lib/Target/Hexagon/HexagonScheduleV66.td
Normal file
@ -0,0 +1,41 @@
|
||||
//=-HexagonScheduleV66.td - HexagonV66 Scheduling Definitions *- tablegen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//
|
||||
// ScalarItin and HVXItin contain some old itineraries
|
||||
// still used by a handful of instructions. Hopefully, we will be able
|
||||
// to get rid of them soon.
|
||||
|
||||
def HexagonV66ItinList : DepScalarItinV66, ScalarItin,
|
||||
DepHVXItinV66, HVXItin, PseudoItin {
|
||||
list<InstrItinData> ItinList =
|
||||
!listconcat(DepScalarItinV66_list, ScalarItin_list,
|
||||
DepHVXItinV66_list, HVXItin_list, PseudoItin_list);
|
||||
}
|
||||
|
||||
def HexagonItinerariesV66 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
|
||||
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
|
||||
CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
|
||||
CVI_ALL_NOMEM, CVI_ZW],
|
||||
[Hex_FWD, HVX_FWD],
|
||||
HexagonV66ItinList.ItinList>;
|
||||
|
||||
def HexagonModelV66 : SchedMachineModel {
|
||||
// Max issue per cycle == bundle width.
|
||||
let IssueWidth = 4;
|
||||
let Itineraries = HexagonItinerariesV66;
|
||||
let LoadLatency = 1;
|
||||
let CompleteModel = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Hexagon V66 Resource Definitions -
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -26,7 +26,7 @@ namespace llvm {
|
||||
/// instruction info tracks.
|
||||
namespace HexagonII {
|
||||
unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY;
|
||||
unsigned const TypeCVI_LAST = TypeCVI_VX_LATE;
|
||||
unsigned const TypeCVI_LAST = TypeCVI_ZW;
|
||||
|
||||
enum SubTarget {
|
||||
HasV55SubT = 0x3c,
|
||||
|
||||
19
test/CodeGen/Hexagon/dfp.ll
Normal file
19
test/CodeGen/Hexagon/dfp.ll
Normal file
@ -0,0 +1,19 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: df_add:
|
||||
; CHECK: dfadd
|
||||
define double @df_add(double %x, double %y) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%add = fadd double %x, %y
|
||||
ret double %add
|
||||
}
|
||||
|
||||
; CHECK-LABEL: df_sub:
|
||||
; CHECK: dfsub
|
||||
define double @df_sub(double %x, double %y) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%sub = fsub double %x, %y
|
||||
ret double %sub
|
||||
}
|
||||
|
||||
attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" }
|
||||
15
test/CodeGen/Hexagon/mnaci_v66.ll
Normal file
15
test/CodeGen/Hexagon/mnaci_v66.ll
Normal file
@ -0,0 +1,15 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
; This test validates the generation of v66 only instruction M2_mnaci
|
||||
; CHECK: r{{[0-9]+}} -= mpyi(r{{[0-9]+}},r{{[0-9]+}})
|
||||
|
||||
target triple = "hexagon-unknown--elf"
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {
|
||||
entry:
|
||||
%mul = mul nsw i32 %c, %b
|
||||
%sub = sub nsw i32 %a, %mul
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" "target-features"="-hvx,-long-calls" }
|
||||
5
test/MC/Hexagon/quad_regs.s
Normal file
5
test/MC/Hexagon/quad_regs.s
Normal file
@ -0,0 +1,5 @@
|
||||
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
|
||||
|
||||
# Test for quad register parsing and printing
|
||||
# CHECK: { v3:0.w = vrmpyz(v0.b,r0.b) }
|
||||
v3:0.w = vrmpyz(v0.b,r0.b)
|
||||
17
test/MC/Hexagon/v66.s
Normal file
17
test/MC/Hexagon/v66.s
Normal file
@ -0,0 +1,17 @@
|
||||
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
|
||||
|
||||
# CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
|
||||
{
|
||||
v4.w = vsatdw(v2.w, v3.w)
|
||||
vmem(r16+#0) = v4.new
|
||||
}
|
||||
|
||||
# CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
|
||||
v1:0.w = vasrinto(v5.w, v10.w)
|
||||
|
||||
# CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
|
||||
v1:0 = vasrinto(v5, v10)
|
||||
|
||||
# CHECK: 1d89ef14 { v20.w = vadd(v15.w,v9.w,q0):carry:sat }
|
||||
v20.w = vadd(v15.w, v9.w, q0):carry:sat
|
||||
|
||||
17
test/MC/Hexagon/z-instructions.s
Normal file
17
test/MC/Hexagon/z-instructions.s
Normal file
@ -0,0 +1,17 @@
|
||||
# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck --implicit-check-not='{' %s
|
||||
|
||||
# CHECK: 2d00c000 { z = vmem(r0++#0) }
|
||||
z = vmem(r0++#0)
|
||||
|
||||
# CHECK-NEXT: 2c00c000 { z = vmem(r0+#0) }
|
||||
z = vmem(r0+#0)
|
||||
|
||||
# CHECK-NEXT: 2d00c001 { z = vmem(r0++m0) }
|
||||
z = vmem(r0++m0)
|
||||
|
||||
# CHECK-NEXT: { v3:0.w += vrmpyz(v13.b,r3.b++)
|
||||
# CHECK-NEXT: v13.tmp = vmem(r2++#1)
|
||||
# CHECK-NEXT: z = vmem(r3+#0) }
|
||||
{ v13.tmp = vmem(r2++#1)
|
||||
v3:0.w += vrmpyz(v13.b,r3.b++)
|
||||
z = vmem(r3+#0) }
|
||||
Loading…
Reference in New Issue
Block a user