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[X86] Enable isel to fold broadcast loads that have been bitcasted from FP into a vpternlog.

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llvm-svn: 373157
This commit is contained in:
Craig Topper 2019-09-29 01:24:33 +00:00
parent 0bed363d8a
commit 9c39cbffb4
2 changed files with 101 additions and 10 deletions
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96
lib/Target/X86/X86InstrAVX512.td
View File

@ -11436,6 +11436,102 @@ defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", SchedWriteVecALU,
defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", SchedWriteVecALU,
avx512vl_i64_info>, VEX_W;
// Patterns to fold bitcasted FP broadcasts.
// FIXME: Need better DAG canonicalization.
let Predicates = [HasVLX] in {
def : Pat<(X86vpternlog VR128X:$src1, VR128X:$src2,
(bc_v4i32 (v4f32 (X86VBroadcast (loadf32 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGDZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v4i32 (v4f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR128X:$src2, VR128X:$src1, (i8 timm:$src4)),
(VPTERNLOGDZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR128X:$src1,
(bc_v4i32 (v4f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR128X:$src2, (i8 timm:$src4)),
(VPTERNLOGDZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR128X:$src1, VR128X:$src2,
(bc_v2i64 (v2f64 (X86VBroadcast (loadf64 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGQZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v2i64 (v2f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR128X:$src2, VR128X:$src1, (i8 timm:$src4)),
(VPTERNLOGQZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR128X:$src1,
(bc_v2i64 (v2f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR128X:$src2, (i8 timm:$src4)),
(VPTERNLOGQZ128rmbi VR128X:$src1, VR128X:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR256X:$src1, VR256X:$src2,
(bc_v8i32 (v8f32 (X86VBroadcast (loadf32 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGDZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v8i32 (v8f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR256X:$src2, VR256X:$src1, (i8 timm:$src4)),
(VPTERNLOGDZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR256X:$src1,
(bc_v8i32 (v8f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR256X:$src2, (i8 timm:$src4)),
(VPTERNLOGDZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR256X:$src1, VR256X:$src2,
(bc_v4i64 (v4f64 (X86VBroadcast (loadf64 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGQZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v4i64 (v4f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR256X:$src2, VR256X:$src1, (i8 timm:$src4)),
(VPTERNLOGQZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR256X:$src1,
(bc_v4i64 (v4f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR256X:$src2, (i8 timm:$src4)),
(VPTERNLOGQZ256rmbi VR256X:$src1, VR256X:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
}
let Predicates = [HasAVX512] in {
def : Pat<(X86vpternlog VR512:$src1, VR512:$src2,
(bc_v16i32 (v16f32 (X86VBroadcast (loadf32 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGDZrmbi VR512:$src1, VR512:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v16i32 (v16f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR512:$src2, VR512:$src1, (i8 timm:$src4)),
(VPTERNLOGDZrmbi VR512:$src1, VR512:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR512:$src1,
(bc_v16i32 (v16f32 (X86VBroadcast (loadf32 addr:$src3)))),
VR512:$src2, (i8 timm:$src4)),
(VPTERNLOGDZrmbi VR512:$src1, VR512:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR512:$src1, VR512:$src2,
(bc_v8i64 (v8f64 (X86VBroadcast (loadf64 addr:$src3)))),
(i8 timm:$src4)),
(VPTERNLOGQZrmbi VR512:$src1, VR512:$src2, addr:$src3,
timm:$src4)>;
def : Pat<(X86vpternlog (bc_v8i64 (v8f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR512:$src2, VR512:$src1, (i8 timm:$src4)),
(VPTERNLOGQZrmbi VR512:$src1, VR512:$src2, addr:$src3,
(VPTERNLOG321_imm8 timm:$src4))>;
def : Pat<(X86vpternlog VR512:$src1,
(bc_v8i64 (v8f64 (X86VBroadcast (loadf64 addr:$src3)))),
VR512:$src2, (i8 timm:$src4)),
(VPTERNLOGQZrmbi VR512:$src1, VR512:$src2, addr:$src3,
(VPTERNLOG132_imm8 timm:$src4))>;
}
// Patterns to use VPTERNLOG for vXi16/vXi8 vectors.
let Predicates = [HasVLX] in {
def : Pat<(v16i8 (X86vpternlog VR128X:$src1, VR128X:$src2, VR128X:$src3,

15
test/CodeGen/X86/vec-copysign-avx512.ll
View File

@ -5,8 +5,7 @@
define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: v4f32:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpbroadcastd {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: vpternlogd $226, %xmm1, %xmm2, %xmm0
; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to4}, %xmm1, %xmm0
; CHECK-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
ret <4 x float> %tmp
@ -15,8 +14,7 @@ define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
; CHECK-LABEL: v8f32:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpbroadcastd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; CHECK-NEXT: vpternlogd $226, %ymm1, %ymm2, %ymm0
; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to8}, %ymm1, %ymm0
; CHECK-NEXT: retq
%tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
ret <8 x float> %tmp
@ -25,8 +23,7 @@ define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
; CHECK-LABEL: v16f32:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpbroadcastd {{.*#+}} zmm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; CHECK-NEXT: vpternlogd $226, %zmm1, %zmm2, %zmm0
; CHECK-NEXT: vpternlogd $228, {{.*}}(%rip){1to16}, %zmm1, %zmm0
; CHECK-NEXT: retq
%tmp = tail call <16 x float> @llvm.copysign.v16f32( <16 x float> %a, <16 x float> %b )
ret <16 x float> %tmp
@ -44,8 +41,7 @@ define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
; CHECK-LABEL: v4f64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpbroadcastq {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: vpternlogq $226, %ymm1, %ymm2, %ymm0
; CHECK-NEXT: vpternlogq $228, {{.*}}(%rip){1to4}, %ymm1, %ymm0
; CHECK-NEXT: retq
%tmp = tail call <4 x double> @llvm.copysign.v4f64( <4 x double> %a, <4 x double> %b )
ret <4 x double> %tmp
@ -54,8 +50,7 @@ define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
define <8 x double> @v8f64(<8 x double> %a, <8 x double> %b) nounwind {
; CHECK-LABEL: v8f64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpbroadcastq {{.*#+}} zmm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; CHECK-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm0
; CHECK-NEXT: vpternlogq $228, {{.*}}(%rip){1to8}, %zmm1, %zmm0
; CHECK-NEXT: retq
%tmp = tail call <8 x double> @llvm.copysign.v8f64( <8 x double> %a, <8 x double> %b )
ret <8 x double> %tmp