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32-to-64-bit sign extension pattern.

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llvm-svn: 146995
This commit is contained in:
Akira Hatanaka 2011-12-20 22:06:20 +00:00
parent dba6358adc
commit 9c5e4d3b90
2 changed files with 8 additions and 0 deletions
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2
lib/Target/Mips/Mips64InstrInfo.td
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@ -299,3 +299,5 @@ def : Pat<(i32 (trunc CPU64Regs:$src)),
// 32-to-64-bit extension
def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;

6
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -293,6 +293,12 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
case ISD::ConstantFP: {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
if (Subtarget.hasMips64()) {
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
Mips::ZERO_64, MVT::i64);
return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
}
SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
Mips::ZERO, MVT::i32);
return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,