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https://github.com/RPCS3/llvm-mirror.git
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[mips][microMIPS] Revert commits r264245 and r264248.
Commit r264245 was the reason for failing tests in LLVM test suite. Commit r264248 depends on the first one. llvm-svn: 265249
This commit is contained in:
Zoran Jovanovic
parent
a8ee5e215e
commit
9cae055d65
@ -513,27 +513,10 @@ class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
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class WAIT_MMR6_DESC : WaitMM<"wait">;
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class SSNOP_MMR6_DESC : Barrier<"ssnop">;
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class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
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class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
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SDPatternOperator OpNode=null_frag>
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: MipsR6Inst {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
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string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
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list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
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string BaseOpcode = opstr;
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Format f = FrmR;
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let isCommutable = 0;
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let isReMaterializable = 1;
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// This instruction doesn't trap division by zero itself. We must insert
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// teq instructions as well.
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bit usesCustomInserter = 1;
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}
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class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>;
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class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>;
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class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>;
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class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>;
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class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
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class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
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class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
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class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
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class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
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class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>;
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class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
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@ -71,16 +71,16 @@ class POOL32S_DALIGN_FM_MMR6 {
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class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rt;
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bits<5> rs;
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0b010110;
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let Inst{25-21} = rt;
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let Inst{25-21} = rd;
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let Inst{20-16} = rs;
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let Inst{15-11} = rd;
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let Inst{15-11} = rt;
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let Inst{10-9} = 0b00;
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let Inst{8-0} = funct;
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}
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@ -94,10 +94,10 @@ class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
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class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
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class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>;
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class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
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class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>;
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class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
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class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
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class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
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class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
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class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
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uimm5_inssize_plus1, MipsIns>;
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@ -49,7 +49,7 @@ def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
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class mem_mm_4_generic : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm4);
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let MIOperandInfo = (ops GPRMM16, simm4);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
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}
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@ -75,7 +75,7 @@ def MicroMipsMemSPAsmOperand : AsmOperandClass {
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def mem_mm_sp_imm5_lsl2 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc:$base, simm5:$offset);
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let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemSPAsmOperand;
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let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
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@ -90,7 +90,7 @@ def mem_mm_gp_imm7_lsl2 : Operand<i32> {
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def mem_mm_9 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm9);
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let MIOperandInfo = (ops GPR32, simm9);
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let EncoderMethod = "getMemEncodingMMImm9";
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let ParserMatchClass = MipsMemSimm9AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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@ -98,7 +98,7 @@ def mem_mm_9 : Operand<i32> {
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def mem_mm_12 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm12);
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let MIOperandInfo = (ops GPR32, simm12);
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let EncoderMethod = "getMemEncodingMMImm12";
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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@ -106,7 +106,7 @@ def mem_mm_12 : Operand<i32> {
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def mem_mm_16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm16);
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let MIOperandInfo = (ops GPR32, simm16);
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let EncoderMethod = "getMemEncodingMMImm16";
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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@ -122,7 +122,7 @@ def MipsMemUimm4AsmOperand : AsmOperandClass {
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def mem_mm_4sp : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, uimm8);
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let MIOperandInfo = (ops GPR32, uimm8);
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let EncoderMethod = "getMemEncodingMMImm4sp";
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let ParserMatchClass = MipsMemUimm4AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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@ -203,7 +203,7 @@ def movep_regpair : Operand<i32> {
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let ParserMatchClass = MovePRegPairAsmOperand;
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let PrintMethod = "printRegisterList";
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let DecoderMethod = "DecodeMovePRegPair";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
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}
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class MovePMM16<string opstr, RegisterOperand RO> :
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@ -224,7 +224,7 @@ def regpair : Operand<i32> {
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let ParserMatchClass = RegPairAsmOperand;
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let PrintMethod = "printRegisterPair";
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let DecoderMethod = "DecodeRegPairOperand";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
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}
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class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
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@ -696,9 +696,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x26c>;
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def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
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MULT_FM_MM<0x2ac>;
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def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
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MULT_FM_MM<0x2ec>;
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/// Arithmetic Instructions with PC and Immediate
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def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
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@ -998,11 +998,6 @@ class UncondBranchMMPseudo<string opstr> :
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def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
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def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
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II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
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II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
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def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
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@ -746,10 +746,8 @@ def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
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def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
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defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
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defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
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def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
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}
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def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
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def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
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def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
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def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
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def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
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@ -771,10 +769,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
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def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
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}
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def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
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def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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@ -220,12 +220,10 @@ def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
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II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
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def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
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}
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def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
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def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
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II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
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@ -91,13 +91,11 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
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def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
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def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
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def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
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}
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def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
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def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
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def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
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def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
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def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
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def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
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def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
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def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
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@ -908,7 +908,7 @@ addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
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static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
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MachineBasicBlock &MBB,
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const TargetInstrInfo &TII,
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bool Is64Bit, bool IsMicroMips) {
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bool Is64Bit) {
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if (NoZeroDivCheck)
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return &MBB;
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@ -916,8 +916,7 @@ static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
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MachineBasicBlock::iterator I(MI);
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MachineInstrBuilder MIB;
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MachineOperand &Divisor = MI->getOperand(2);
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MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(),
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TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
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MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
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.addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
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.addReg(Mips::ZERO).addImm(7);
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@ -1017,29 +1016,14 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case Mips::DIVU:
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case Mips::MOD:
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case Mips::MODU:
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
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false);
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case Mips::SDIV_MM_Pseudo:
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case Mips::UDIV_MM_Pseudo:
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case Mips::SDIV_MM:
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case Mips::UDIV_MM:
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case Mips::DIV_MMR6:
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case Mips::DIVU_MMR6:
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case Mips::MOD_MMR6:
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case Mips::MODU_MMR6:
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
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case Mips::PseudoDSDIV:
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case Mips::PseudoDUDIV:
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case Mips::DDIV:
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case Mips::DDIVU:
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case Mips::DMOD:
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case Mips::DMODU:
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
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case Mips::DDIV_MM64R6:
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case Mips::DDIVU_MM64R6:
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case Mips::DMOD_MM64R6:
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case Mips::DMODU_MM64R6:
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
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case Mips::SEL_D:
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return emitSEL_D(MI, BB);
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@ -1913,12 +1913,11 @@ def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
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def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
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def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
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}
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def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
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def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
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MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
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def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
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ISA_MIPS1_NOT_32R6_64R6;
|
||||
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
|
||||
@ -1986,12 +1985,12 @@ def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
|
||||
ISA_MIPS32_NOT_32R6_64R6;
|
||||
}
|
||||
|
||||
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
|
||||
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
|
||||
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
|
||||
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
|
||||
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
||||
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
|
||||
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
|
||||
}
|
||||
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
|
||||
def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
|
||||
@ -2333,10 +2332,10 @@ def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
||||
def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
||||
"divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
|
||||
|
||||
def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
|
||||
def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
||||
"ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
|
||||
|
||||
def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
|
||||
def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
||||
"ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
|
||||
|
||||
def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
|
||||
|
||||
@ -42,9 +42,7 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() {
|
||||
STI.inMips16Mode()
|
||||
? &Mips::CPU16RegsRegClass
|
||||
: STI.inMicroMipsMode()
|
||||
? STI.hasMips64()
|
||||
? &Mips::GPRMM16_64RegClass
|
||||
: &Mips::GPRMM16RegClass
|
||||
? &Mips::GPRMM16RegClass
|
||||
: static_cast<const MipsTargetMachine &>(MF.getTarget())
|
||||
.getABI()
|
||||
.IsN64()
|
||||
|
||||
@ -330,12 +330,6 @@ def GPR64 : RegisterClass<"Mips", [i64], 64, (add
|
||||
// Reserved
|
||||
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
|
||||
|
||||
def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add
|
||||
// Callee save
|
||||
S0_64, S1_64,
|
||||
// Return Values and Arguments
|
||||
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>;
|
||||
|
||||
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
|
||||
// Return Values and Arguments
|
||||
V0, V1, A0, A1, A2, A3,
|
||||
|
||||
@ -24,12 +24,6 @@
|
||||
; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefix=R6 -check-prefix=64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
|
||||
|
||||
define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
@ -48,17 +42,6 @@ entry:
|
||||
; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; R6: sra $2, $[[T1]], 31
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; MMR3: sra $2, $[[T1]], 31
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; MMR6: sra $2, $[[T1]], 31
|
||||
|
||||
%r = sdiv i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
@ -85,15 +68,6 @@ entry:
|
||||
; FIXME: This instruction is redundant.
|
||||
; R6: seb $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T0]]
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seb $2, $[[T0]]
|
||||
|
||||
%r = sdiv i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
@ -120,15 +94,6 @@ entry:
|
||||
; FIXME: This is instruction is redundant since div is signed.
|
||||
; R6: seh $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $[[T0:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T0]]
|
||||
|
||||
; MMR6: div $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seh $2, $[[T0]]
|
||||
|
||||
%r = sdiv i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
@ -144,13 +109,6 @@ entry:
|
||||
; R6: div $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: div $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = sdiv i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
@ -168,11 +126,6 @@ entry:
|
||||
; 64R6: ddiv $2, $4, $5
|
||||
; 64R6: teq $5, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__divdi3)($2)
|
||||
|
||||
; MM64: ddiv $2, $4, $5
|
||||
; MM64: teq $5, $zero, 7
|
||||
|
||||
%r = sdiv i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
@ -181,185 +134,11 @@ define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__divti3)($gp)
|
||||
; GP32: lw $25, %call16(__divti3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
|
||||
; 64R6: ld $25, %call16(__divti3)($gp)
|
||||
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
|
||||
; 64R6: ld $25, %call16(__divti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__divti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__divti3)($2)
|
||||
|
||||
%r = sdiv i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define signext i1 @sdiv_0_i1(i1 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i8:
|
||||
|
||||
; NOT-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R6: mflo $[[T1:[0-9]+]]
|
||||
; NOT-R6: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; NOT-R6: sra $2, $[[T2]], 31
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; R6: sra $2, $[[T1]], 31
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mflo $[[T1:[0-9]+]]
|
||||
; MMR3: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; MMR3: sra $2, $[[T2]], 31
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: div $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; MMR6: sra $2, $[[T2]], 31
|
||||
|
||||
%r = sdiv i1 %a, 0
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @sdiv_0_i8(i8 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i8:
|
||||
|
||||
; NOT-R2-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R2-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R2-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R2-R6: mflo $[[T1:[0-9]+]]
|
||||
; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24
|
||||
; NOT-R2-R6: sra $2, $[[T2]], 24
|
||||
|
||||
; R2-R5: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; R2-R5: div $zero, $4, $[[T0]]
|
||||
; R2-R5: teq $[[T0]], $zero, 7
|
||||
; R2-R5: mflo $[[T1:[0-9]+]]
|
||||
; R2-R5: seb $2, $[[T1]]
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: seb $2, $[[T0]]
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mflo $[[T1:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T1]]
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: div $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seb $2, $[[T1]]
|
||||
|
||||
%r = sdiv i8 %a, 0
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @sdiv_0_i16(i16 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i16:
|
||||
|
||||
; NOT-R2-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R2-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R2-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R2-R6: mflo $[[T1:[0-9]+]]
|
||||
; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16
|
||||
; NOT-R2-R6: sra $2, $[[T2]], 16
|
||||
|
||||
; R2-R5: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; R2-R5: div $zero, $4, $[[T0]]
|
||||
; R2-R5: teq $[[T0]], $zero, 7
|
||||
; R2-R5: mflo $[[T1:[0-9]+]]
|
||||
; R2-R5: seh $2, $[[T1]]
|
||||
|
||||
; R6: div $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: seh $2, $[[T0]]
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mflo $[[T1:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T1]]
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: div $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seh $2, $[[T1]]
|
||||
|
||||
%r = sdiv i16 %a, 0
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
define signext i32 @sdiv_0_i32(i32 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i32:
|
||||
|
||||
; NOT-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R6: mflo $2
|
||||
|
||||
; R6: div $2, $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: div $2, $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
|
||||
%r = sdiv i32 %a, 0
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @sdiv_0_i64(i64 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i64:
|
||||
|
||||
; GP32: lw $25, %call16(__divdi3)($gp)
|
||||
|
||||
; GP64-NOT-R6: daddiu $[[T0:[0-9]+]], $zero, 0
|
||||
; GP64-NOT-R6: ddiv $zero, $4, $[[T0]]
|
||||
; GP64-NOT-R6: teq $[[T0]], $zero, 7
|
||||
; GP64-NOT-R6: mflo $2
|
||||
|
||||
; 64R6: ddiv $2, $4, $zero
|
||||
; 64R6: teq $zero, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__divdi3)($2)
|
||||
|
||||
; MM64: ddiv $2, $4, $zero
|
||||
; MM64: teq $zero, $zero, 7
|
||||
|
||||
%r = sdiv i64 %a, 0
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @sdiv_0_i128(i128 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: sdiv_0_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__divti3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
|
||||
; 64R6: ld $25, %call16(__divti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__divti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__divti3)($2)
|
||||
|
||||
%r = sdiv i128 %a, 0
|
||||
ret i128 %r
|
||||
%r = sdiv i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
@ -27,12 +27,6 @@
|
||||
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
|
||||
|
||||
define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
@ -49,17 +43,6 @@ entry:
|
||||
; R6: sll $[[T3:[0-9]+]], $[[T0]], 31
|
||||
; R6: sra $2, $[[T3]], 31
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mfhi $[[T0:[0-9]+]]
|
||||
; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; MMR3: sra $2, $[[T1]], 31
|
||||
|
||||
; MMR6: mod $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; MMR6: sra $2, $[[T1]], 31
|
||||
|
||||
%r = srem i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
@ -83,15 +66,6 @@ entry:
|
||||
; R6: teq $5, $zero, 7
|
||||
; R6: seb $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mfhi $[[T0:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T0]]
|
||||
|
||||
; MMR6: mod $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seb $2, $[[T0]]
|
||||
|
||||
%r = srem i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
@ -109,21 +83,12 @@ entry:
|
||||
; R2-R5: div $zero, $4, $5
|
||||
; R2-R5: teq $5, $zero, 7
|
||||
; R2-R5: mfhi $[[T0:[0-9]+]]
|
||||
; R2-R5: seh $2, $[[T0]]
|
||||
; R2-R5: seh $2, $[[T1]]
|
||||
|
||||
; R6: mod $[[T0:[0-9]+]], $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
; R6: seh $2, $[[T0]]
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mfhi $[[T0:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T0]]
|
||||
|
||||
; MMR6: mod $[[T0:[0-9]+]], $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
; MMR6: seh $2, $[[T0]]
|
||||
|
||||
%r = srem i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
@ -139,13 +104,6 @@ entry:
|
||||
; R6: mod $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: div $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mfhi $2
|
||||
|
||||
; MMR6: mod $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = srem i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
@ -163,11 +121,6 @@ entry:
|
||||
; 64R6: dmod $2, $4, $5
|
||||
; 64R6: teq $5, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__moddi3)($2)
|
||||
|
||||
; MM64: dmod $2, $4, $5
|
||||
; MM64: teq $5, $zero, 7
|
||||
|
||||
%r = srem i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
@ -181,181 +134,6 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
|
||||
; 64-R6: ld $25, %call16(__modti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__modti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__modti3)($2)
|
||||
|
||||
%r = srem i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
define signext i1 @srem_0_i1(i1 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i1:
|
||||
|
||||
; NOT-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R6: mfhi $[[T1:[0-9]+]]
|
||||
; NOT-R6: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; NOT-R6: sra $2, $[[T2]], 31
|
||||
|
||||
; R6: mod $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
|
||||
; R6: sra $2, $[[T1]], 31
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T1:[0-9]+]]
|
||||
; MMR3: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; MMR3: sra $2, $[[T2]], 31
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: mod $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: sll $[[T2:[0-9]+]], $[[T1]], 31
|
||||
; MMR6: sra $2, $[[T2]], 31
|
||||
|
||||
%r = srem i1 %a, 0
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
define signext i8 @srem_0_i8(i8 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i8:
|
||||
|
||||
; NOT-R2-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R2-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R2-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R2-R6: mfhi $[[T1:[0-9]+]]
|
||||
; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24
|
||||
; NOT-R2-R6: sra $2, $[[T2]], 24
|
||||
|
||||
; R2-R5: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; R2-R5: div $zero, $4, $[[T0]]
|
||||
; R2-R5: teq $[[T0]], $zero, 7
|
||||
; R2-R5: mfhi $[[T1:[0-9]+]]
|
||||
; R2-R5: seb $2, $[[T1]]
|
||||
|
||||
; R6: mod $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: seb $2, $[[T0]]
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T1:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T1]]
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: mod $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seb $2, $[[T1]]
|
||||
|
||||
%r = srem i8 %a, 0
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
define signext i16 @srem_0_i16(i16 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i16:
|
||||
|
||||
; NOT-R2-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R2-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R2-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R2-R6: mfhi $[[T1:[0-9]+]]
|
||||
; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16
|
||||
; NOT-R2-R6: sra $2, $[[T2]], 16
|
||||
|
||||
; R2-R5: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; R2-R5: div $zero, $4, $[[T0]]
|
||||
; R2-R5: teq $[[T0]], $zero, 7
|
||||
; R2-R5: mfhi $[[T1:[0-9]+]]
|
||||
; R2-R5: seh $2, $[[T1]]
|
||||
|
||||
; R6: mod $[[T0:[0-9]+]], $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
; R6: seh $2, $[[T0]]
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T1:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T1]]
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: mod $[[T1:[0-9]+]], $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seh $2, $[[T1]]
|
||||
|
||||
%r = srem i16 %a, 0
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
|
||||
define signext i32 @srem_0_i32(i32 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i32:
|
||||
|
||||
; NOT-R6: addiu $[[T0:[0-9]+]], $zero, 0
|
||||
; NOT-R6: div $zero, $4, $[[T0]]
|
||||
; NOT-R6: teq $[[T0]], $zero, 7
|
||||
; NOT-R6: mfhi $2
|
||||
|
||||
; R6: mod $2, $4, $zero
|
||||
; R6: teq $zero, $zero, 7
|
||||
|
||||
; MMR3: lui $[[T0:[0-9]+]], 0
|
||||
; MMR3: div $zero, $4, $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $2
|
||||
|
||||
; MMR6: lui $[[T0:[0-9]+]], 0
|
||||
; MMR6: mod $2, $4, $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
|
||||
%r = srem i32 %a, 0
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define signext i64 @srem_0_i64(i64 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i64:
|
||||
|
||||
; GP32: lw $25, %call16(__moddi3)($gp)
|
||||
|
||||
; GP64-NOT-R6: daddiu $[[T0:[0-9]+]], $zero, 0
|
||||
; GP64-NOT-R6: ddiv $zero, $4, $[[T0]]
|
||||
; GP64-NOT-R6: teq $[[T0]], $zero, 7
|
||||
; GP64-NOT-R6: mfhi $2
|
||||
|
||||
; 64R6: dmod $2, $4, $zero
|
||||
; 64R6: teq $zero, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__moddi3)($2)
|
||||
|
||||
; MM64: dmod $2, $4, $zero
|
||||
; MM64: teq $zero, $zero, 7
|
||||
|
||||
%r = srem i64 %a, 0
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
define signext i128 @srem_0_i128(i128 signext %a) {
|
||||
entry:
|
||||
; ALL-LABEL: srem_0_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__modti3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
|
||||
; 64R6: ld $25, %call16(__modti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__modti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__modti3)($2)
|
||||
|
||||
%r = srem i128 %a, 0
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
@ -24,12 +24,6 @@
|
||||
; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefix=R6 -check-prefix=64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
|
||||
|
||||
define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
|
||||
entry:
|
||||
@ -42,13 +36,6 @@ entry:
|
||||
; R6: divu $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: divu $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: divu $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = udiv i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
@ -64,13 +51,6 @@ entry:
|
||||
; R6: divu $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: divu $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: divu $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = udiv i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
@ -86,13 +66,6 @@ entry:
|
||||
; R6: divu $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: divu $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: divu $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = udiv i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
@ -108,13 +81,6 @@ entry:
|
||||
; R6: divu $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: divu $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mflo $2
|
||||
|
||||
; MMR6: divu $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = udiv i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
@ -132,11 +98,6 @@ entry:
|
||||
; 64R6: ddivu $2, $4, $5
|
||||
; 64R6: teq $5, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__udivdi3)($2)
|
||||
|
||||
; MM64: ddivu $2, $4, $5
|
||||
; MM64: teq $5, $zero, 7
|
||||
|
||||
%r = udiv i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
@ -150,10 +111,6 @@ entry:
|
||||
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
|
||||
; 64-R6: ld $25, %call16(__udivti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__udivti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__udivti3)($2)
|
||||
|
||||
%r = udiv i128 %a, %b
|
||||
ret i128 %r
|
||||
}
|
||||
|
||||
@ -27,12 +27,6 @@
|
||||
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR3 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM32
|
||||
; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: -check-prefix=MM -check-prefix=MMR6 -check-prefix=MM64
|
||||
|
||||
define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
|
||||
entry:
|
||||
@ -53,21 +47,6 @@ entry:
|
||||
; R6: sll $[[T3:[0-9]+]], $[[T2]], 31
|
||||
; R6: sra $2, $[[T3]], 31
|
||||
|
||||
; MMR3: andi16 $[[T0:[0-9]+]], $5, 1
|
||||
; MMR3: andi16 $[[T1:[0-9]+]], $4, 1
|
||||
; MMR3: divu $zero, $[[T1]], $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T2:[0-9]+]]
|
||||
; MMR3: sll $[[T3:[0-9]+]], $[[T2]], 31
|
||||
; MMR3: sra $2, $[[T3]], 31
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $5, 1
|
||||
; MMR6: andi16 $[[T1:[0-9]+]], $4, 1
|
||||
; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: sll $[[T3:[0-9]+]], $[[T2]], 31
|
||||
; MMR6: sra $2, $[[T3]], 31
|
||||
|
||||
%r = urem i1 %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
@ -97,19 +76,6 @@ entry:
|
||||
; R6: teq $[[T0]], $zero, 7
|
||||
; R6: seb $2, $[[T2]]
|
||||
|
||||
; MMR3: andi16 $[[T0:[0-9]+]], $5, 255
|
||||
; MMR3: andi16 $[[T1:[0-9]+]], $4, 255
|
||||
; MMR3: divu $zero, $[[T1]], $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T2:[0-9]+]]
|
||||
; MMR3: seb $2, $[[T2]]
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $5, 255
|
||||
; MMR6: andi16 $[[T1:[0-9]+]], $4, 255
|
||||
; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seb $2, $[[T2]]
|
||||
|
||||
%r = urem i8 %a, %b
|
||||
ret i8 %r
|
||||
}
|
||||
@ -139,19 +105,6 @@ entry:
|
||||
; R6: teq $[[T0]], $zero, 7
|
||||
; R6: seh $2, $[[T2]]
|
||||
|
||||
; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535
|
||||
; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535
|
||||
; MMR3: divu $zero, $[[T1]], $[[T0]]
|
||||
; MMR3: teq $[[T0]], $zero, 7
|
||||
; MMR3: mfhi $[[T2:[0-9]+]]
|
||||
; MMR3: seh $2, $[[T2]]
|
||||
|
||||
; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535
|
||||
; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535
|
||||
; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
|
||||
; MMR6: teq $[[T0]], $zero, 7
|
||||
; MMR6: seh $2, $[[T2]]
|
||||
|
||||
%r = urem i16 %a, %b
|
||||
ret i16 %r
|
||||
}
|
||||
@ -167,13 +120,6 @@ entry:
|
||||
; R6: modu $2, $4, $5
|
||||
; R6: teq $5, $zero, 7
|
||||
|
||||
; MMR3: divu $zero, $4, $5
|
||||
; MMR3: teq $5, $zero, 7
|
||||
; MMR3: mfhi $2
|
||||
|
||||
; MMR6: modu $2, $4, $5
|
||||
; MMR6: teq $5, $zero, 7
|
||||
|
||||
%r = urem i32 %a, %b
|
||||
ret i32 %r
|
||||
}
|
||||
@ -191,11 +137,6 @@ entry:
|
||||
; 64R6: dmodu $2, $4, $5
|
||||
; 64R6: teq $5, $zero, 7
|
||||
|
||||
; MM32: lw $25, %call16(__umoddi3)($2)
|
||||
|
||||
; MM64: dmodu $2, $4, $5
|
||||
; MM64: teq $5, $zero, 7
|
||||
|
||||
%r = urem i64 %a, %b
|
||||
ret i64 %r
|
||||
}
|
||||
@ -204,14 +145,10 @@ define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
|
||||
entry:
|
||||
; ALL-LABEL: urem_i128:
|
||||
|
||||
; GP32: lw $25, %call16(__umodti3)($gp)
|
||||
; GP32: lw $25, %call16(__umodti3)($gp)
|
||||
|
||||
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
|
||||
; 64-R6: ld $25, %call16(__umodti3)($gp)
|
||||
|
||||
; MM32: lw $25, %call16(__umodti3)($2)
|
||||
|
||||
; MM64: ld $25, %call16(__umodti3)($2)
|
||||
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
|
||||
; 64-R6: ld $25, %call16(__umodti3)($gp)
|
||||
|
||||
%r = urem i128 %a, %b
|
||||
ret i128 %r
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
|
||||
; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
|
||||
@x = global i32 65504, align 4
|
||||
@y = global i32 60929, align 4
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
|
||||
; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
|
||||
@x = global i32 65504, align 4
|
||||
@y = global i32 60929, align 4
|
||||
|
||||
@ -1,8 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
; For microMIPS64, also check 32 to 64 bit registers and 64 to 32 bit register copies
|
||||
; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips \
|
||||
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
|
||||
|
||||
@g = external global i32
|
||||
|
||||
|
||||
@ -28,10 +28,10 @@
|
||||
0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
|
||||
0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
|
||||
0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
|
||||
0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
|
||||
0x58 0xa4 0x19 0x58 # CHECK: dmod $3, $4, $5
|
||||
0x58 0xa4 0x19 0x98 # CHECK: ddivu $3, $4, $5
|
||||
0x58 0xa4 0x19 0xd8 # CHECK: dmodu $3, $4, $5
|
||||
0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5
|
||||
0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5
|
||||
0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5
|
||||
0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5
|
||||
0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5
|
||||
0x54 0xc4 0x11 0x30 # CHECK: add.d $f2, $f4, $f6
|
||||
0x54 0xa4 0x18 0x70 # CHECK: sub.s $f3, $f4, $f5
|
||||
|
||||
@ -27,10 +27,10 @@ a:
|
||||
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
|
||||
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
|
||||
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
|
||||
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
|
||||
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58]
|
||||
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
|
||||
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0xd8]
|
||||
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18]
|
||||
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0x64,0x29,0x58]
|
||||
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98]
|
||||
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0x64,0x29,0xd8]
|
||||
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
|
||||
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
|
||||
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user