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RegPressure: Fix crash on blocks with only dbg_value
If there were only dbg_values in the block, recede would hit the beginning of the block and try to use thet dbg_value as a real instruction. llvm-svn: 357105
This commit is contained in:
Matt Arsenault
parent
fefcede6ab
commit
9cc632cfab
@ -845,7 +845,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
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CurrPos = skipDebugInstructionsBackward(std::prev(CurrPos), MBB->begin());
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SlotIndex SlotIdx;
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if (RequireIntervals)
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if (RequireIntervals && !CurrPos->isDebugInstr())
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SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
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// Open the top of the region using slot indexes.
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@ -855,6 +855,12 @@ void RegPressureTracker::recedeSkipDebugValues() {
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void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
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recedeSkipDebugValues();
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if (CurrPos->isDebugValue()) {
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// It's possible to only have debug_value instructions and hit the start of
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// the block.
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assert(CurrPos == MBB->begin());
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return;
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}
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const MachineInstr &MI = *CurrPos;
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RegisterOperands RegOpers;
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135
test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
Normal file
135
test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
Normal file
@ -0,0 +1,135 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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define amdgpu_kernel void @could_not_use_debug_inst_to_query_mi2mimap() #1 {
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ret void
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}
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declare hidden float @foo(float, float, float) local_unnamed_addr #1
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attributes #0 = { nounwind readnone speculatable }
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attributes #1 = {nounwind }
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...
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---
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name: could_not_use_debug_inst_to_query_mi2mimap
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tracksRegLiveness: true
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frameInfo:
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hasCalls: true
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body: |
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; CHECK-LABEL: name: could_not_use_debug_inst_to_query_mi2mimap
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 1082130432, [[DEF1]], implicit $exec
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; CHECK: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: DBG_VALUE
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; CHECK: DBG_VALUE
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; CHECK: DBG_VALUE
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: S_BRANCH %bb.3
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; CHECK: bb.3:
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
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; CHECK: [[V_MUL_F32_e32_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
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; CHECK: [[V_MUL_F32_e32_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
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; CHECK: [[V_MUL_F32_e32_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
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; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
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; CHECK: [[DEF13:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[V_ADD_F32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
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; CHECK: [[V_MUL_F32_e32_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
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; CHECK: dead %23:vgpr_32 = V_MUL_F32_e32 [[V_MUL_F32_e32_4]], [[DEF13]], implicit $exec
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; CHECK: dead [[V_MOV_B32_e32_1]]:vgpr_32 = V_MAC_F32_e32 [[V_ADD_F32_e32_]], [[COPY]], [[V_MOV_B32_e32_1]], implicit $exec
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; CHECK: [[DEF14:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; CHECK: $sgpr4 = IMPLICIT_DEF
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; CHECK: $vgpr0 = COPY [[DEF11]]
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; CHECK: $vgpr0 = COPY [[V_MOV_B32_e32_]]
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; CHECK: $vgpr1 = COPY [[DEF7]]
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; CHECK: $vgpr0 = COPY [[V_MUL_F32_e32_1]]
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; CHECK: $vgpr1 = COPY [[V_MUL_F32_e32_2]]
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; CHECK: $vgpr2 = COPY [[V_MUL_F32_e32_3]]
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; CHECK: dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0
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; CHECK: [[V_ADD_F32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MUL_F32_e32_]], [[DEF8]], implicit $exec
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; CHECK: [[V_MAC_F32_e32_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e32 [[DEF12]], [[DEF9]], [[V_MAC_F32_e32_]], implicit $exec
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; CHECK: dead %26:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $exec
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; CHECK: dead %27:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $exec
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; CHECK: dead %28:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $exec
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; CHECK: GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, implicit $exec
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; CHECK: S_ENDPGM 0
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bb.0:
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successors: %bb.1
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%0:vreg_64 = IMPLICIT_DEF
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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%5:vgpr_32 = IMPLICIT_DEF
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%6:vgpr_32 = IMPLICIT_DEF
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%7:vgpr_32 = IMPLICIT_DEF
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%8:vgpr_32 = IMPLICIT_DEF
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%9:vgpr_32 = V_MUL_F32_e32 1082130432, %1, implicit $exec
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%10:vgpr_32 = IMPLICIT_DEF
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%11:vgpr_32 = IMPLICIT_DEF
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bb.1:
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successors: %bb.2
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DBG_VALUE
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DBG_VALUE
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DBG_VALUE
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bb.2:
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successors: %bb.3
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S_BRANCH %bb.3
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bb.3:
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%12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%13:vgpr_32 = COPY %12
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%14:vgpr_32 = IMPLICIT_DEF
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%15:vgpr_32 = IMPLICIT_DEF
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%16:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
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%17:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
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%18:vgpr_32 = V_MUL_F32_e32 %12, %12, implicit $exec
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%19:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
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%20:vgpr_32 = IMPLICIT_DEF
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%21:vgpr_32 = V_ADD_F32_e32 %12, %12, implicit $exec
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%22:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
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%23:vgpr_32 = V_MUL_F32_e32 %22, %20, implicit $exec
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%19:vgpr_32 = V_MAC_F32_e32 %21, %13, %19, implicit $exec
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%24:sreg_64 = IMPLICIT_DEF
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$vgpr0 = COPY %14
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$vgpr0 = COPY %12
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$vgpr1 = COPY %7
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$vgpr0 = COPY %16
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$vgpr1 = COPY %17
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$vgpr2 = COPY %18
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$sgpr4 = IMPLICIT_DEF
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dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0
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%25:vgpr_32 = V_ADD_F32_e32 %9, %8, implicit $exec
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%25:vgpr_32 = V_MAC_F32_e32 %15, %10, %25, implicit $exec
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%26:vgpr_32 = V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $exec
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%27:vgpr_32 = V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $exec
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%28:vgpr_32 = V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $exec
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GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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