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[PowerPC] Implement trap and conversion builtins for XL compatibility
This patch implements trap and FP to and from double conversions. The builtins generate code that mirror what is generated from the XL compiler. Intrinsics are named conventionally with builtin_ppc, but are aliased to provide the same builtin names as the XL compiler. Differential Revision: https://reviews.llvm.org/D103668
This commit is contained in:
Albion Fung
parent
6ee8270ba3
commit
9cfb434c49
@ -112,9 +112,45 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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: GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
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Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
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// Intrinsics defined to maintain XL compatibility
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def int_ppc_tdw
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: GCCBuiltin<"__builtin_ppc_tdw">,
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Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
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def int_ppc_tw
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: GCCBuiltin<"__builtin_ppc_tw">,
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Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
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def int_ppc_trapd
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: GCCBuiltin<"__builtin_ppc_trapd">,
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Intrinsic <[], [llvm_i64_ty], []>;
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def int_ppc_trap
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: GCCBuiltin<"__builtin_ppc_trap">,
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Intrinsic <[], [llvm_i32_ty], []>;
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def int_ppc_fcfid
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: GCCBuiltin<"__builtin_ppc_fcfid">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fcfud
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: GCCBuiltin<"__builtin_ppc_fcfud">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctid
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: GCCBuiltin<"__builtin_ppc_fctid">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctidz
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: GCCBuiltin<"__builtin_ppc_fctidz">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctiw
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: GCCBuiltin<"__builtin_ppc_fctiw">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctiwz
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: GCCBuiltin<"__builtin_ppc_fctiwz">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctudz
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: GCCBuiltin<"__builtin_ppc_fctudz">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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def int_ppc_fctuwz
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: GCCBuiltin<"__builtin_ppc_fctuwz">,
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Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
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}
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let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
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/// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
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class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
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@ -1725,3 +1725,9 @@ def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
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(STDCX g8rc:$A, ForceXForm:$dst)>;
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def : Pat<(int_ppc_ldarx ForceXForm:$dst),
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(LDARX ForceXForm:$dst)>;
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def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
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(TD $IMM, $A, $B)>;
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// trapd
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def : Pat<(int_ppc_trapd g8rc:$A),
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(TDI 24, $A, 0)>;
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@ -5416,3 +5416,24 @@ def : Pat<(int_ppc_lwarx ForceXForm:$dst),
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(LWARX ForceXForm:$dst)>;
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def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
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(STWCX gprc:$A, ForceXForm:$dst)>;
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def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
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(TW $IMM, $A, $B)>;
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def : Pat<(int_ppc_trap gprc:$A),
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(TWI 24, $A, 0)>;
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def : Pat<(int_ppc_fcfid f64:$A),
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(XSCVSXDDP $A)>;
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def : Pat<(int_ppc_fcfud f64:$A),
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(XSCVUXDDP $A)>;
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def : Pat<(int_ppc_fctid f64:$A),
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(FCTID $A)>;
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def : Pat<(int_ppc_fctidz f64:$A),
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(XSCVDPSXDS $A)>;
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def : Pat<(int_ppc_fctiw f64:$A),
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(FCTIW $A)>;
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def : Pat<(int_ppc_fctiwz f64:$A),
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(XSCVDPSXWS $A)>;
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def : Pat<(int_ppc_fctudz f64:$A),
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(XSCVDPUXDS $A)>;
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def : Pat<(int_ppc_fctuwz f64:$A),
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(XSCVDPUXWS $A)>;
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89
test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
Normal file
89
test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
Normal file
@ -0,0 +1,89 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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declare double @llvm.ppc.fcfid(double %a)
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define dso_local double @test_fcfid(double %a) {
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; CHECK-LABEL: test_fcfid:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvsxddp 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fcfid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fcfud(double %a)
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define dso_local double @test_fcfud(double %a) {
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; CHECK-LABEL: test_fcfud:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvuxddp 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fcfud(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctid(double %a)
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define dso_local double @test_fctid(double %a) {
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; CHECK-LABEL: test_fctid:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctidz(double %a)
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define dso_local double @test_fctidz(double %a) {
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; CHECK-LABEL: test_fctidz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctiw(double %a)
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define dso_local double @test_fctiw(double %a) {
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; CHECK-LABEL: test_fctiw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctiwz(double %a)
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define dso_local double @test_fctiwz(double %a) {
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; CHECK-LABEL: test_fctiwz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctudz(double %a)
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define dso_local double @test_fctudz(double %a) {
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; CHECK-LABEL: test_fctudz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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declare double @llvm.ppc.fctuwz(double %a)
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define dso_local double @test_fctuwz(double %a) {
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; CHECK-LABEL: test_fctuwz:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fctid 1, 1
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; CHECK-NEXT: blr
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%1 = call double @llvm.ppc.fctid(double %a)
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ret double %1
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}
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136
test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
Normal file
136
test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
Normal file
@ -0,0 +1,136 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; tdw
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declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
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define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwlgt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdlgt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
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ret void
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}
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define dso_local void @test__tdwllt(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwllt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdllt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
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ret void
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}
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define dso_local void @test__tdw3(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdw3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 3, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)
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ret void
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}
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define dso_local void @test__tdweq(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdweq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdeq 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
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ret void
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}
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define dso_local void @test__tdwlge(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwlge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 5, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
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ret void
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}
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define dso_local void @test__tdwlle(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwlle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 6, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
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ret void
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}
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define dso_local void @test__tdwgt(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwgt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdgt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
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ret void
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}
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define dso_local void @test__tdwge(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 12, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
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ret void
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}
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define dso_local void @test__tdwlt(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwlt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdlt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
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ret void
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}
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define dso_local void @test__tdwle(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 20, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
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ret void
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}
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define dso_local void @test__tdwne24(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdwne24:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdne 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
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ret void
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}
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define dso_local void @test__tdw31(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdw31:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdu 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
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ret void
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}
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define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
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; CHECK-LABEL: test__tdw_no_match:
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; CHECK: # %bb.0:
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; CHECK-NEXT: td 13, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
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ret void
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}
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; trapd
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declare void @llvm.ppc.trapd(i64 %a)
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define dso_local void @test__trapd(i64 %a) {
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; CHECK-LABEL: test__trapd:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tdnei 3, 0
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; CHECK-NEXT: blr
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call void @llvm.ppc.trapd(i64 %a)
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ret void
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}
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139
test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Normal file
139
test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Normal file
@ -0,0 +1,139 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; tw
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declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
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define dso_local void @test__twlgt(i32 %a, i32 %b) {
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; CHECK-LABEL: test__twlgt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: twlgt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
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ret void
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}
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define dso_local void @test__twllt(i32 %a, i32 %b) {
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; CHECK-LABEL: test__twllt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: twllt 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
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ret void
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}
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define dso_local void @test__tw3(i32 %a, i32 %b) {
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; CHECK-LABEL: test__tw3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tw 3, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
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ret void
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}
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define dso_local void @test__tweq(i32 %a, i32 %b) {
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; CHECK-LABEL: test__tweq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tweq 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
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ret void
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}
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define dso_local void @test__twlge(i32 %a, i32 %b) {
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; CHECK-LABEL: test__twlge:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tw 5, 3, 4
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; CHECK-NEXT: blr
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call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
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ret void
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}
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define dso_local void @test__twlle(i32 %a, i32 %b) {
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; CHECK-LABEL: test__twlle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: tw 6, 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twgt(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twgt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: twgt 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twge(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twge:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: tw 12, 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twlt(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twlt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: twlt 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twle(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twle:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: tw 20, 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twne24(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twne24:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: twne 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__twu(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__twu:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: twu 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
|
||||
ret void
|
||||
}
|
||||
|
||||
define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: test__tw_no_match:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: tw 13, 3, 4
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
|
||||
ret void
|
||||
}
|
||||
|
||||
; trap
|
||||
declare void @llvm.ppc.trap(i32 %a)
|
||||
define dso_local void @test__trap(i32 %a) {
|
||||
; CHECK-LABEL: test__trap:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: twnei 3, 0
|
||||
; CHECK-NEXT: blr
|
||||
call void @llvm.ppc.trap(i32 %a)
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user