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Revert "[X86][AVX] Add getBROADCAST_LOAD helper function. NFCI."
This reverts commit 1cfecf4fc4278afb0005923f6dff595cd372da5c. This commit broke LLVM code generated through XLA by removing a conditional on Ld->getExtensionType() == ISD::NON_EXTLOAD
This commit is contained in:
Tres Popp
parent
adf33c8470
commit
9d32182a3a
@ -7988,30 +7988,6 @@ static bool getTargetShuffleInputs(SDValue Op, SmallVectorImpl<SDValue> &Inputs,
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KnownZero, DAG, Depth, ResolveKnownElts);
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}
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// Attempt to create a scalar/subvector broadcast from the base MemSDNode.
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static SDValue getBROADCAST_LOAD(unsigned Opcode, const SDLoc &DL, EVT VT,
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EVT MemVT, MemSDNode *Mem, unsigned Offset,
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SelectionDAG &DAG) {
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assert((Opcode == X86ISD::VBROADCAST_LOAD ||
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Opcode == X86ISD::SUBV_BROADCAST_LOAD) &&
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"Unknown broadcast load type");
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// Ensure this is a simple (non-atomic, non-voltile), temporal read memop.
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if (!Mem || !Mem->readMem() || !Mem->isSimple() || Mem->isNonTemporal())
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return SDValue();
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SDValue Ptr =
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DAG.getMemBasePlusOffset(Mem->getBasePtr(), TypeSize::Fixed(Offset), DL);
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SDVTList Tys = DAG.getVTList(VT, MVT::Other);
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SDValue Ops[] = {Mem->getChain(), Ptr};
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SDValue BcstLd = DAG.getMemIntrinsicNode(
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Opcode, DL, Tys, Ops, MemVT,
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DAG.getMachineFunction().getMachineMemOperand(
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Mem->getMemOperand(), Offset, MemVT.getStoreSize()));
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DAG.makeEquivalentMemoryOrdering(SDValue(Mem, 1), BcstLd.getValue(1));
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return BcstLd;
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}
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/// Returns the scalar element that will make up the i'th
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/// element of the result of the vector shuffle.
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static SDValue getShuffleScalarElt(SDValue Op, unsigned Index,
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@ -16084,12 +16060,21 @@ static SDValue lowerV2X128Shuffle(const SDLoc &DL, MVT VT, SDValue V1,
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bool SplatHi = isShuffleEquivalent(Mask, {2, 3, 2, 3}, V1);
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if ((SplatLo || SplatHi) && !Subtarget.hasAVX512() && V1.hasOneUse() &&
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MayFoldLoad(peekThroughOneUseBitcasts(V1))) {
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MVT MemVT = VT.getHalfNumVectorElementsVT();
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unsigned Ofs = SplatLo ? 0 : MemVT.getStoreSize();
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auto *Ld = cast<LoadSDNode>(peekThroughOneUseBitcasts(V1));
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if (SDValue BcstLd = getBROADCAST_LOAD(X86ISD::SUBV_BROADCAST_LOAD, DL,
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VT, MemVT, Ld, Ofs, DAG))
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return BcstLd;
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if (!Ld->isNonTemporal()) {
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MVT MemVT = VT.getHalfNumVectorElementsVT();
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unsigned Ofs = SplatLo ? 0 : MemVT.getStoreSize();
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SDVTList Tys = DAG.getVTList(VT, MVT::Other);
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SDValue Ptr = DAG.getMemBasePlusOffset(Ld->getBasePtr(),
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TypeSize::Fixed(Ofs), DL);
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SDValue Ops[] = {Ld->getChain(), Ptr};
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SDValue BcastLd = DAG.getMemIntrinsicNode(
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X86ISD::SUBV_BROADCAST_LOAD, DL, Tys, Ops, MemVT,
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DAG.getMachineFunction().getMachineMemOperand(
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Ld->getMemOperand(), Ofs, MemVT.getStoreSize()));
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DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), BcastLd.getValue(1));
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return BcastLd;
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}
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}
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// With AVX2, use VPERMQ/VPERMPD for unary shuffles to allow memory folding.
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@ -38992,10 +38977,10 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
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}
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// Subvector broadcast.
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case X86ISD::SUBV_BROADCAST_LOAD: {
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SDLoc DL(Op);
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auto *MemIntr = cast<MemIntrinsicSDNode>(Op);
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EVT MemVT = MemIntr->getMemoryVT();
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if (ExtSizeInBits == MemVT.getStoreSizeInBits()) {
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SDLoc DL(Op);
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SDValue Ld =
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TLO.DAG.getLoad(MemVT, DL, MemIntr->getChain(),
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MemIntr->getBasePtr(), MemIntr->getMemOperand());
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@ -39004,13 +38989,18 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
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return TLO.CombineTo(Op, insertSubVector(TLO.DAG.getUNDEF(VT), Ld, 0,
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TLO.DAG, DL, ExtSizeInBits));
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} else if ((ExtSizeInBits % MemVT.getStoreSizeInBits()) == 0) {
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SDLoc DL(Op);
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EVT BcstVT = EVT::getVectorVT(*TLO.DAG.getContext(), VT.getScalarType(),
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ExtSizeInBits / VT.getScalarSizeInBits());
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if (SDValue BcstLd =
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getBROADCAST_LOAD(Opc, DL, BcstVT, MemVT, MemIntr, 0, TLO.DAG))
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return TLO.CombineTo(Op,
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insertSubVector(TLO.DAG.getUNDEF(VT), BcstLd, 0,
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TLO.DAG, DL, ExtSizeInBits));
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SDVTList Tys = TLO.DAG.getVTList(BcstVT, MVT::Other);
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SDValue Ops[] = {MemIntr->getOperand(0), MemIntr->getOperand(1)};
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SDValue Bcst =
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TLO.DAG.getMemIntrinsicNode(X86ISD::SUBV_BROADCAST_LOAD, DL, Tys,
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Ops, MemVT, MemIntr->getMemOperand());
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TLO.DAG.makeEquivalentMemoryOrdering(SDValue(MemIntr, 1),
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Bcst.getValue(1));
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return TLO.CombineTo(Op, insertSubVector(TLO.DAG.getUNDEF(VT), Bcst, 0,
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TLO.DAG, DL, ExtSizeInBits));
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}
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break;
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}
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@ -50083,21 +50073,36 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
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if (Op0.getOpcode() == X86ISD::VBROADCAST)
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return DAG.getNode(Op0.getOpcode(), DL, VT, Op0.getOperand(0));
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// If this simple subvector or scalar/subvector broadcast_load is inserted
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// into both halves, use a larger broadcast_load. Update other uses to use
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// an extracted subvector.
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if (Op0.getOpcode() == ISD::LOAD ||
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Op0.getOpcode() == X86ISD::VBROADCAST_LOAD ||
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// If this scalar/subvector broadcast_load is inserted into both halves, use
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// a larger broadcast_load. Update other uses to use an extracted subvector.
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if (Op0.getOpcode() == X86ISD::VBROADCAST_LOAD ||
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Op0.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD) {
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auto *Mem = cast<MemSDNode>(Op0);
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unsigned Opcode = Op0.getOpcode() == X86ISD::VBROADCAST_LOAD
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? X86ISD::VBROADCAST_LOAD
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: X86ISD::SUBV_BROADCAST_LOAD;
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if (SDValue BcastLd = getBROADCAST_LOAD(
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Opcode, DL, VT, Mem->getMemoryVT(), Mem, 0, DAG)) {
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auto *MemIntr = cast<MemIntrinsicSDNode>(Op0);
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SDVTList Tys = DAG.getVTList(VT, MVT::Other);
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SDValue Ops[] = {MemIntr->getChain(), MemIntr->getBasePtr()};
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SDValue BcastLd = DAG.getMemIntrinsicNode(Op0.getOpcode(), DL, Tys, Ops,
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MemIntr->getMemoryVT(),
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MemIntr->getMemOperand());
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DAG.ReplaceAllUsesOfValueWith(
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Op0, extractSubVector(BcastLd, 0, DAG, DL, Op0.getValueSizeInBits()));
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DAG.ReplaceAllUsesOfValueWith(SDValue(MemIntr, 1), BcastLd.getValue(1));
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return BcastLd;
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}
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// If this is a simple subvector load repeated across multiple lanes, then
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// broadcast the load. Update other uses to use an extracted subvector.
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if (auto *Ld = dyn_cast<LoadSDNode>(Op0)) {
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if (Ld->isSimple() && !Ld->isNonTemporal() &&
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Ld->getExtensionType() == ISD::NON_EXTLOAD) {
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SDVTList Tys = DAG.getVTList(VT, MVT::Other);
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SDValue Ops[] = {Ld->getChain(), Ld->getBasePtr()};
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SDValue BcastLd =
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DAG.getMemIntrinsicNode(X86ISD::SUBV_BROADCAST_LOAD, DL, Tys, Ops,
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Ld->getMemoryVT(), Ld->getMemOperand());
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DAG.ReplaceAllUsesOfValueWith(
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Op0,
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extractSubVector(BcastLd, 0, DAG, DL, Op0.getValueSizeInBits()));
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DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), BcastLd.getValue(1));
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return BcastLd;
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}
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}
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@ -50461,8 +50466,14 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
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if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&
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SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) {
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auto *MemIntr = cast<MemIntrinsicSDNode>(SubVec);
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return getBROADCAST_LOAD(X86ISD::VBROADCAST_LOAD, dl, OpVT,
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MemIntr->getMemoryVT(), MemIntr, 0, DAG);
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SDVTList Tys = DAG.getVTList(OpVT, MVT::Other);
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SDValue Ops[] = { MemIntr->getChain(), MemIntr->getBasePtr() };
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SDValue BcastLd =
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DAG.getMemIntrinsicNode(X86ISD::VBROADCAST_LOAD, dl, Tys, Ops,
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MemIntr->getMemoryVT(),
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MemIntr->getMemOperand());
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DAG.ReplaceAllUsesOfValueWith(SDValue(MemIntr, 1), BcastLd.getValue(1));
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return BcastLd;
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}
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// If we're splatting the lower half subvector of a full vector load into the
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