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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00

[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.

If -simplify-mir option is passed then MIRPrinter will not print such fields.
This change also required some lit test cases in CodeGen directory to be changed.

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D32304

llvm-svn: 304779
This commit is contained in:
Vivek Pandya 2017-06-06 08:16:19 +00:00
parent 82c702fbf8
commit 9d4d8b5728
78 changed files with 1540 additions and 1462 deletions

View File

@ -72,6 +72,9 @@ template <> struct ScalarTraits<FlowStringValue> {
struct BlockStringValue {
StringValue Value;
bool operator==(const BlockStringValue &Other) const {
return Value == Other.Value;
}
};
template <> struct BlockScalarTraits<BlockStringValue> {
@ -146,6 +149,10 @@ struct VirtualRegisterDefinition {
StringValue Class;
StringValue PreferredRegister;
// TODO: Serialize the target specific register hints.
bool operator==(const VirtualRegisterDefinition &Other) const {
return ID == Other.ID && Class == Other.Class &&
PreferredRegister == Other.PreferredRegister;
}
};
template <> struct MappingTraits<VirtualRegisterDefinition> {
@ -162,6 +169,10 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
struct MachineFunctionLiveIn {
StringValue Register;
StringValue VirtualRegister;
bool operator==(const MachineFunctionLiveIn &Other) const {
return Register == Other.Register &&
VirtualRegister == Other.VirtualRegister;
}
};
template <> struct MappingTraits<MachineFunctionLiveIn> {
@ -196,6 +207,14 @@ struct MachineStackObject {
StringValue DebugVar;
StringValue DebugExpr;
StringValue DebugLoc;
bool operator==(const MachineStackObject &Other) const {
return ID == Other.ID && Name == Other.Name && Type == Other.Type &&
Offset == Other.Offset && Size == Other.Size &&
Alignment == Other.Alignment &&
CalleeSavedRegister == Other.CalleeSavedRegister &&
LocalOffset == Other.LocalOffset && DebugVar == Other.DebugVar &&
DebugExpr == Other.DebugExpr && DebugLoc == Other.DebugLoc;
}
};
template <> struct ScalarEnumerationTraits<MachineStackObject::ObjectType> {
@ -214,13 +233,13 @@ template <> struct MappingTraits<MachineStackObject> {
YamlIO.mapOptional(
"type", Object.Type,
MachineStackObject::DefaultType); // Don't print the default type.
YamlIO.mapOptional("offset", Object.Offset);
YamlIO.mapOptional("offset", Object.Offset, (int64_t)0);
if (Object.Type != MachineStackObject::VariableSized)
YamlIO.mapRequired("size", Object.Size);
YamlIO.mapOptional("alignment", Object.Alignment);
YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister,
StringValue()); // Don't print it out when it's empty.
YamlIO.mapOptional("local-offset", Object.LocalOffset);
YamlIO.mapOptional("local-offset", Object.LocalOffset, Optional<int64_t>());
YamlIO.mapOptional("di-variable", Object.DebugVar,
StringValue()); // Don't print it out when it's empty.
YamlIO.mapOptional("di-expression", Object.DebugExpr,
@ -244,6 +263,12 @@ struct FixedMachineStackObject {
bool IsImmutable = false;
bool IsAliased = false;
StringValue CalleeSavedRegister;
bool operator==(const FixedMachineStackObject &Other) const {
return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
Size == Other.Size && Alignment == Other.Alignment &&
IsImmutable == Other.IsImmutable && IsAliased == Other.IsAliased &&
CalleeSavedRegister == Other.CalleeSavedRegister;
}
};
template <>
@ -261,12 +286,12 @@ template <> struct MappingTraits<FixedMachineStackObject> {
YamlIO.mapOptional(
"type", Object.Type,
FixedMachineStackObject::DefaultType); // Don't print the default type.
YamlIO.mapOptional("offset", Object.Offset);
YamlIO.mapOptional("size", Object.Size);
YamlIO.mapOptional("alignment", Object.Alignment);
YamlIO.mapOptional("offset", Object.Offset, (int64_t)0);
YamlIO.mapOptional("size", Object.Size, (uint64_t)0);
YamlIO.mapOptional("alignment", Object.Alignment, (unsigned)0);
if (Object.Type != FixedMachineStackObject::SpillSlot) {
YamlIO.mapOptional("isImmutable", Object.IsImmutable);
YamlIO.mapOptional("isAliased", Object.IsAliased);
YamlIO.mapOptional("isImmutable", Object.IsImmutable, false);
YamlIO.mapOptional("isAliased", Object.IsAliased, false);
}
YamlIO.mapOptional("callee-saved-register", Object.CalleeSavedRegister,
StringValue()); // Don't print it out when it's empty.
@ -279,13 +304,17 @@ struct MachineConstantPoolValue {
UnsignedValue ID;
StringValue Value;
unsigned Alignment = 0;
bool operator==(const MachineConstantPoolValue &Other) const {
return ID == Other.ID && Value == Other.Value &&
Alignment == Other.Alignment;
}
};
template <> struct MappingTraits<MachineConstantPoolValue> {
static void mapping(IO &YamlIO, MachineConstantPoolValue &Constant) {
YamlIO.mapRequired("id", Constant.ID);
YamlIO.mapOptional("value", Constant.Value);
YamlIO.mapOptional("alignment", Constant.Alignment);
YamlIO.mapOptional("value", Constant.Value, StringValue());
YamlIO.mapOptional("alignment", Constant.Alignment, (unsigned)0);
}
};
@ -293,16 +322,22 @@ struct MachineJumpTable {
struct Entry {
UnsignedValue ID;
std::vector<FlowStringValue> Blocks;
bool operator==(const Entry &Other) const {
return ID == Other.ID && Blocks == Other.Blocks;
}
};
MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32;
std::vector<Entry> Entries;
bool operator==(const MachineJumpTable &Other) const {
return Kind == Other.Kind && Entries == Other.Entries;
}
};
template <> struct MappingTraits<MachineJumpTable::Entry> {
static void mapping(IO &YamlIO, MachineJumpTable::Entry &Entry) {
YamlIO.mapRequired("id", Entry.ID);
YamlIO.mapOptional("blocks", Entry.Blocks);
YamlIO.mapOptional("blocks", Entry.Blocks, std::vector<FlowStringValue>());
}
};
@ -322,7 +357,8 @@ namespace yaml {
template <> struct MappingTraits<MachineJumpTable> {
static void mapping(IO &YamlIO, MachineJumpTable &JT) {
YamlIO.mapRequired("kind", JT.Kind);
YamlIO.mapOptional("entries", JT.Entries);
YamlIO.mapOptional("entries", JT.Entries,
std::vector<MachineJumpTable::Entry>());
}
};
@ -351,25 +387,43 @@ struct MachineFrameInfo {
bool HasMustTailInVarArgFunc = false;
StringValue SavePoint;
StringValue RestorePoint;
bool operator==(const MachineFrameInfo &Other) const {
return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
IsReturnAddressTaken == Other.IsReturnAddressTaken &&
HasStackMap == Other.HasStackMap &&
HasPatchPoint == Other.HasPatchPoint &&
StackSize == Other.StackSize &&
OffsetAdjustment == Other.OffsetAdjustment &&
MaxAlignment == Other.MaxAlignment &&
AdjustsStack == Other.AdjustsStack && HasCalls == Other.HasCalls &&
StackProtector == Other.StackProtector &&
MaxCallFrameSize == Other.MaxCallFrameSize &&
HasOpaqueSPAdjustment == Other.HasOpaqueSPAdjustment &&
HasVAStart == Other.HasVAStart &&
HasMustTailInVarArgFunc == Other.HasMustTailInVarArgFunc &&
SavePoint == Other.SavePoint && RestorePoint == Other.RestorePoint;
}
};
template <> struct MappingTraits<MachineFrameInfo> {
static void mapping(IO &YamlIO, MachineFrameInfo &MFI) {
YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken);
YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken);
YamlIO.mapOptional("hasStackMap", MFI.HasStackMap);
YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint);
YamlIO.mapOptional("stackSize", MFI.StackSize);
YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment);
YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment);
YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack);
YamlIO.mapOptional("hasCalls", MFI.HasCalls);
YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken, false);
YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken, false);
YamlIO.mapOptional("hasStackMap", MFI.HasStackMap, false);
YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint, false);
YamlIO.mapOptional("stackSize", MFI.StackSize, (uint64_t)0);
YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment, (int)0);
YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment, (unsigned)0);
YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack, false);
YamlIO.mapOptional("hasCalls", MFI.HasCalls, false);
YamlIO.mapOptional("stackProtector", MFI.StackProtector,
StringValue()); // Don't print it out when it's empty.
YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, ~0u);
YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment);
YamlIO.mapOptional("hasVAStart", MFI.HasVAStart);
YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc);
YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize, (unsigned)~0);
YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment,
false);
YamlIO.mapOptional("hasVAStart", MFI.HasVAStart, false);
YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc,
false);
YamlIO.mapOptional("savePoint", MFI.SavePoint,
StringValue()); // Don't print it out when it's empty.
YamlIO.mapOptional("restorePoint", MFI.RestorePoint,
@ -403,22 +457,28 @@ struct MachineFunction {
template <> struct MappingTraits<MachineFunction> {
static void mapping(IO &YamlIO, MachineFunction &MF) {
YamlIO.mapRequired("name", MF.Name);
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("registers", MF.VirtualRegisters);
YamlIO.mapOptional("liveins", MF.LiveIns);
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);
YamlIO.mapOptional("frameInfo", MF.FrameInfo);
YamlIO.mapOptional("fixedStack", MF.FixedStackObjects);
YamlIO.mapOptional("stack", MF.StackObjects);
YamlIO.mapOptional("constants", MF.Constants);
YamlIO.mapOptional("alignment", MF.Alignment, (unsigned)0);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice, false);
YamlIO.mapOptional("legalized", MF.Legalized, false);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false);
YamlIO.mapOptional("selected", MF.Selected, false);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
YamlIO.mapOptional("registers", MF.VirtualRegisters,
std::vector<VirtualRegisterDefinition>());
YamlIO.mapOptional("liveins", MF.LiveIns,
std::vector<MachineFunctionLiveIn>());
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters,
Optional<std::vector<FlowStringValue>>());
YamlIO.mapOptional("frameInfo", MF.FrameInfo, MachineFrameInfo());
YamlIO.mapOptional("fixedStack", MF.FixedStackObjects,
std::vector<FixedMachineStackObject>());
YamlIO.mapOptional("stack", MF.StackObjects,
std::vector<MachineStackObject>());
YamlIO.mapOptional("constants", MF.Constants,
std::vector<MachineConstantPoolValue>());
if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())
YamlIO.mapOptional("jumpTable", MF.JumpTableInfo);
YamlIO.mapOptional("body", MF.Body);
YamlIO.mapOptional("jumpTable", MF.JumpTableInfo, MachineJumpTable());
YamlIO.mapOptional("body", MF.Body, BlockStringValue());
}
};

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@ -210,6 +210,8 @@ void MIRPrinter::print(const MachineFunction &MF) {
}
StrOS.flush();
yaml::Output Out(OS);
if (!SimplifyMIR)
Out.setWriteDefaultValues(true);
Out << YamlMF;
}

View File

@ -4,7 +4,7 @@
; CHECK: name: test_stack_guard
; CHECK: stack:
; CHECK: - { id: 0, name: StackGuardSlot, offset: 0, size: 8, alignment: 8 }
; CHECK: - { id: 0, name: StackGuardSlot, type: default, offset: 0, size: 8, alignment: 8,
; CHECK-NOT: id: 1
; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot

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@ -31,10 +31,13 @@ define i64 @muli64(i64 %arg1, i64 %arg2) {
; Tests for alloca
; CHECK-LABEL: name: allocai64
; CHECK: stack:
; CHECK-NEXT: - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 }
; CHECK-NEXT: - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 }
; CHECK-NEXT: - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 }
; CHECK-NEXT: - { id: 3, name: ptr4, offset: 0, size: 1, alignment: 8 }
; CHECK-NEXT: - { id: 0, name: ptr1, type: default, offset: 0, size: 8, alignment: 8,
; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
; CHECK-NEXT: - { id: 1, name: ptr2, type: default, offset: 0, size: 8, alignment: 1,
; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
; CHECK-NEXT: - { id: 2, name: ptr3, type: default, offset: 0, size: 128, alignment: 8,
; CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
; CHECK-NEXT: - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3

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@ -98,8 +98,8 @@ name: defaultMapping
legalized: true
# CHECK-LABEL: name: defaultMapping
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -119,8 +119,8 @@ name: defaultMappingVector
legalized: true
# CHECK-LABEL: name: defaultMappingVector
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -141,10 +141,10 @@ name: defaultMapping1Repair
legalized: true
# CHECK-LABEL: name: defaultMapping1Repair
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -166,10 +166,10 @@ name: defaultMapping2Repairs
legalized: true
# CHECK-LABEL: name: defaultMapping2Repairs
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -193,9 +193,9 @@ name: defaultMappingDefRepair
legalized: true
# CHECK-LABEL: name: defaultMappingDefRepair
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: fpr }
@ -215,11 +215,11 @@ name: phiPropagation
legalized: true
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr64sp }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 4, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr64sp }
@ -254,10 +254,10 @@ name: defaultMappingUseRepairPhysReg
legalized: true
# CHECK-LABEL: name: defaultMappingUseRepairPhysReg
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -280,8 +280,8 @@ name: defaultMappingDefRepairPhysReg
legalized: true
# CHECK-LABEL: name: defaultMappingDefRepairPhysReg
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -303,18 +303,18 @@ name: greedyMappingOr
legalized: true
# CHECK-LABEL: name: greedyMappingOr
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# Fast mode maps vector instruction on FPR.
# FAST-NEXT: - { id: 2, class: fpr }
# FAST-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# Fast mode needs two extra copies.
# FAST-NEXT: - { id: 3, class: fpr }
# FAST-NEXT: - { id: 4, class: fpr }
# FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# Greedy mode coalesce the computation on the GPR register
# because it is the cheapest.
# GREEDY-NEXT: - { id: 2, class: gpr }
# GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -350,18 +350,18 @@ name: greedyMappingOrWithConstraints
legalized: true
# CHECK-LABEL: name: greedyMappingOrWithConstraints
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: fpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# Fast mode maps vector instruction on FPR.
# Fast mode needs two extra copies.
# FAST-NEXT: - { id: 3, class: fpr }
# FAST-NEXT: - { id: 4, class: fpr }
# FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# Greedy mode coalesce the computation on the GPR register because it
# is the cheapest, but will need one extra copy to materialize %2 into a FPR.
# GREEDY-NEXT: - { id: 3, class: gpr }
# GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -396,8 +396,8 @@ body: |
name: ignoreTargetSpecificInst
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr64 }
- { id: 1, class: gpr64 }
@ -434,8 +434,8 @@ name: bitcast_s32_gpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -457,8 +457,8 @@ name: bitcast_s32_fpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# CHECK-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -480,9 +480,9 @@ name: bitcast_s32_gpr_fpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# FAST-NEXT: - { id: 1, class: fpr }
# GREEDY-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -504,9 +504,9 @@ name: bitcast_s32_fpr_gpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# FAST-NEXT: - { id: 1, class: gpr }
# GREEDY-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -528,8 +528,8 @@ name: bitcast_s64_gpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -551,8 +551,8 @@ name: bitcast_s64_fpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# CHECK-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -574,9 +574,9 @@ name: bitcast_s64_gpr_fpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# FAST-NEXT: - { id: 1, class: fpr }
# GREEDY-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: fpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -597,9 +597,9 @@ name: bitcast_s64_fpr_gpr
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# FAST-NEXT: - { id: 1, class: gpr }
# GREEDY-NEXT: - { id: 1, class: fpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -624,15 +624,15 @@ name: greedyWithChainOfComputation
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# FAST-NEXT: - { id: 2, class: fpr }
# FAST-NEXT: - { id: 3, class: fpr }
# FAST-NEXT: - { id: 4, class: fpr }
# GREEDY-NEXT: - { id: 2, class: gpr }
# GREEDY-NEXT: - { id: 3, class: gpr }
# GREEDY-NEXT: - { id: 4, class: gpr }
# CHECK-NEXT: - { id: 5, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# FAST-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# FAST-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -674,11 +674,11 @@ name: floatingPointLoad
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: fpr }
# CHECK-NEXT: - { id: 3, class: fpr }
# CHECK-NEXT: - { id: 4, class: fpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -716,11 +716,11 @@ name: floatingPointStore
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: fpr }
# CHECK-NEXT: - { id: 3, class: fpr }
# CHECK-NEXT: - { id: 4, class: fpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -3,8 +3,8 @@
; CHECK-LABEL: name: test_stack_slots
; CHECK: fixedStack:
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 1
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 1, size: 1
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]

View File

@ -35,7 +35,7 @@ define void @test_simple_arg(i32 %in) {
; CHECK-LABEL: name: test_indirect_call
; CHECK: registers:
; Make sure the register feeding the indirect call is properly constrained.
; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64 }
; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
; CHECK: %[[FUNC]](p0) = COPY %x0
; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
; CHECK: RET_ReallyLR
@ -165,9 +165,9 @@ define zeroext i8 @test_abi_zext_ret(i8* %addr) {
; CHECK-LABEL: name: test_stack_slots
; CHECK: fixedStack:
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 8
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 8, size: 8
; CHECK-DAG: - { id: [[STACK16:[0-9]+]], offset: 16, size: 8
; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8,
; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
@ -208,7 +208,7 @@ define void @test_call_stack() {
; CHECK-LABEL: name: test_mem_i1
; CHECK: fixedStack:
; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
define void @test_mem_i1([8 x i64], i1 %in) {

View File

@ -3,8 +3,8 @@
; CHECK-LABEL: name: debug_declare
; CHECK: stack:
; CHECK: - { id: {{.*}}, name: in.addr, offset: {{.*}}, size: {{.*}}, alignment: {{.*}}, di-variable: '!11',
; CHECK-NEXT: di-expression: '!12', di-location: '!13' }
; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
; CHECK-NEXT: callee-saved-register: '', di-variable: '!11', di-expression: '!12',
; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13
define void @debug_declare(i32 %in) #0 !dbg !7 {
entry:

View File

@ -35,15 +35,15 @@ regBankSelected: true
tracksRegLiveness: true
registers:
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: fpr }
# CHECK-NEXT: - { id: 3, class: fpr }
# CHECK-NEXT: - { id: 4, class: fpr }
# CHECK-NEXT: - { id: 5, class: fpr }
# CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
# The localizer will create two new values to materialize the constants.
# OPTNONE-NEXT: - { id: 6, class: fpr }
# OPTNONE-NEXT: - { id: 7, class: fpr }
# OPTNONE-NEXT: - { id: 6, class: fpr, preferred-register: '' }
# OPTNONE-NEXT: - { id: 7, class: fpr, preferred-register: '' }
- { id: 0, class: fpr }
- { id: 1, class: gpr }
- { id: 2, class: fpr }

View File

@ -44,11 +44,11 @@ regBankSelected: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: gpr }
#CHECK-NEXT: - { id: 1, class: gpr }
#CHECK-NEXT: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 3, class: gpr }
#CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -82,11 +82,11 @@ regBankSelected: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: gpr }
#CHECK-NEXT: - { id: 1, class: gpr }
#CHECK-NEXT: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 3, class: gpr }
#CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -120,13 +120,13 @@ tracksRegLiveness: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: gpr }
#CHECK-NEXT: - { id: 1, class: gpr }
#CHECK-NEXT: - { id: 2, class: gpr }
#CHECK-NEXT: - { id: 3, class: gpr }
#CHECK-NEXT: - { id: 4, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 5, class: gpr }
#CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -168,14 +168,14 @@ tracksRegLiveness: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: gpr }
#CHECK-NEXT: - { id: 1, class: gpr }
#CHECK-NEXT: - { id: 2, class: gpr }
#CHECK-NEXT: - { id: 3, class: gpr }
#CHECK-NEXT: - { id: 4, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# The newly created regs should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 5, class: gpr }
#CHECK-NEXT: - { id: 6, class: gpr }
#CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -219,14 +219,14 @@ tracksRegLiveness: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: gpr }
#CHECK-NEXT: - { id: 1, class: gpr }
#CHECK-NEXT: - { id: 2, class: gpr }
#CHECK-NEXT: - { id: 3, class: gpr }
#CHECK-NEXT: - { id: 4, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 5, class: gpr }
#CHECK-NEXT: - { id: 6, class: gpr }
#CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
#CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -270,14 +270,14 @@ tracksRegLiveness: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: fpr }
#CHECK-NEXT: - { id: 1, class: fpr }
#CHECK-NEXT: - { id: 2, class: fpr }
#CHECK-NEXT: - { id: 3, class: fpr }
#CHECK-NEXT: - { id: 4, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 5, class: fpr }
#CHECK-NEXT: - { id: 6, class: fpr }
#CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 6, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: fpr }
@ -323,12 +323,12 @@ tracksRegLiveness: true
# CHECK: registers:
# Existing registers should be left untouched
# CHECK: - { id: 0, class: fpr }
#CHECK-NEXT: - { id: 1, class: fpr }
#CHECK-NEXT: - { id: 2, class: fpr }
#CHECK-NEXT: - { id: 3, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 1, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
#CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
# The newly created reg should be on the same regbank/regclass as its origin.
#CHECK-NEXT: - { id: 4, class: fpr }
#CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: fpr }

View File

@ -32,7 +32,7 @@
name: test_dbg_value
legalized: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
body: |
bb.0:
liveins: %w0

View File

@ -73,8 +73,8 @@
name: test_add_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -92,8 +92,8 @@ body: |
name: test_add_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -111,8 +111,8 @@ body: |
name: test_sub_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -130,8 +130,8 @@ body: |
name: test_sub_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -149,8 +149,8 @@ body: |
name: test_mul_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -168,8 +168,8 @@ body: |
name: test_mul_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -187,8 +187,8 @@ body: |
name: test_and_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -206,8 +206,8 @@ body: |
name: test_and_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -225,8 +225,8 @@ body: |
name: test_or_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -244,8 +244,8 @@ body: |
name: test_or_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -263,8 +263,8 @@ body: |
name: test_xor_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -282,8 +282,8 @@ body: |
name: test_xor_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -301,8 +301,8 @@ body: |
name: test_shl_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -320,8 +320,8 @@ body: |
name: test_shl_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -339,8 +339,8 @@ body: |
name: test_lshr_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -358,8 +358,8 @@ body: |
name: test_ashr_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -377,8 +377,8 @@ body: |
name: test_sdiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -396,8 +396,8 @@ body: |
name: test_udiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -415,8 +415,8 @@ body: |
name: test_anyext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -434,8 +434,8 @@ body: |
name: test_sext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -453,8 +453,8 @@ body: |
name: test_zext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -472,8 +472,8 @@ body: |
name: test_trunc_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -491,7 +491,7 @@ body: |
name: test_constant_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
body: |
@ -505,7 +505,7 @@ body: |
name: test_constant_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
body: |
@ -519,8 +519,8 @@ body: |
name: test_icmp_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -538,8 +538,8 @@ body: |
name: test_icmp_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -557,7 +557,7 @@ body: |
name: test_frame_index_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
stack:
@ -573,8 +573,8 @@ body: |
name: test_ptrtoint_s64_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -592,8 +592,8 @@ body: |
name: test_inttoptr_p0_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -611,8 +611,8 @@ body: |
name: test_load_s32_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -630,8 +630,8 @@ body: |
name: test_store_s32_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -651,8 +651,8 @@ body: |
name: test_fadd_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -670,8 +670,8 @@ body: |
name: test_fsub_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -689,8 +689,8 @@ body: |
name: test_fmul_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -708,8 +708,8 @@ body: |
name: test_fdiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -727,8 +727,8 @@ body: |
name: test_fpext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -746,8 +746,8 @@ body: |
name: test_fptrunc_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -765,7 +765,7 @@ body: |
name: test_fconstant_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
body: |
@ -779,8 +779,8 @@ body: |
name: test_fcmp_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -798,8 +798,8 @@ body: |
name: test_sitofp_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -817,8 +817,8 @@ body: |
name: test_uitofp_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -836,8 +836,8 @@ body: |
name: test_fptosi_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -855,8 +855,8 @@ body: |
name: test_fptoui_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: fpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -64,9 +64,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -94,9 +94,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -123,9 +123,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr32sp }
# CHECK-NEXT: - { id: 0, class: gpr32sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32sp, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -151,9 +151,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr64sp }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64sp, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -179,9 +179,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr32sp }
# CHECK-NEXT: - { id: 0, class: gpr32sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32sp, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -213,9 +213,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -243,9 +243,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -273,9 +273,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -303,9 +303,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -333,9 +333,9 @@ legalized: true
regBankSelected: true
#
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -365,9 +365,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -395,9 +395,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -425,9 +425,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -455,9 +455,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -485,9 +485,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -515,9 +515,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -545,9 +545,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -575,9 +575,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -606,9 +606,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -636,9 +636,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -666,10 +666,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 3, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr64, preferred-register: '' }
# CHECK: body:
# CHECK: %0 = COPY %x0
@ -696,9 +696,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -726,9 +726,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -756,9 +756,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -786,9 +786,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -816,9 +816,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 2, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -845,9 +845,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -874,9 +874,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 2, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -903,9 +903,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -932,9 +932,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 2, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -961,9 +961,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -990,9 +990,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 2, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -1019,9 +1019,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }

View File

@ -19,8 +19,8 @@ name: bitcast_s32_gpr
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32all }
# CHECK-NEXT: - { id: 1, class: gpr32all }
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -44,8 +44,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -69,8 +69,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32all }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -94,8 +94,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32all }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -119,8 +119,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64all }
# CHECK-NEXT: - { id: 1, class: gpr64all }
# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -144,8 +144,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -169,8 +169,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64all }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -193,8 +193,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64all }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }

View File

@ -34,8 +34,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr64 }
# CHECK: - { id: 1, class: fpr32 }
# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -59,8 +59,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr32 }
# CHECK: - { id: 1, class: fpr64 }
# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
@ -84,8 +84,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -109,8 +109,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -134,8 +134,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -159,8 +159,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -184,8 +184,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -209,8 +209,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -234,8 +234,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -259,8 +259,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -284,8 +284,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -309,8 +309,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -334,8 +334,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -359,8 +359,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -384,8 +384,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -409,8 +409,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -434,8 +434,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -459,8 +459,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }

View File

@ -24,9 +24,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32all }
# CHECK-NEXT: - { id: 1, class: gpr64all }
# CHECK-NEXT: - { id: 2, class: gpr64all }
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64all, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -51,8 +51,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32all }
# CHECK-NEXT: - { id: 1, class: gpr32all }
# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -76,9 +76,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -103,8 +103,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -128,8 +128,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -153,8 +153,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -178,9 +178,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -205,8 +205,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -230,8 +230,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -255,8 +255,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -18,8 +18,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64all }
# CHECK-NEXT: - { id: 1, class: gpr64all }
# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -41,8 +41,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -64,8 +64,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -87,8 +87,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -110,8 +110,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -133,8 +133,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -37,8 +37,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -62,8 +62,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -87,8 +87,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -112,8 +112,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -137,8 +137,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -165,10 +165,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -197,10 +197,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -229,10 +229,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -261,10 +261,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -293,8 +293,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -318,8 +318,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -343,8 +343,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr16 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -368,8 +368,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr8 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -393,10 +393,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -425,10 +425,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -457,10 +457,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: fpr16 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -489,10 +489,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: fpr8 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: fpr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -13,13 +13,13 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 4, class: gpr }
# CHECK-NEXT: - { id: 5, class: gpr }
# CHECK-NEXT: - { id: 6, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 6, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -35,8 +35,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -62,8 +62,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -89,8 +89,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -116,8 +116,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -143,8 +143,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -169,8 +169,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -195,8 +195,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -223,10 +223,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -255,10 +255,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -287,10 +287,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -319,10 +319,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -351,8 +351,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -378,8 +378,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -405,10 +405,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr64 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }
@ -437,10 +437,10 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 1, class: fpr32 }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: fpr }

View File

@ -15,8 +15,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -39,8 +39,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -63,8 +63,8 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -20,9 +20,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -50,9 +50,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr64 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -81,9 +81,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -110,9 +110,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64 }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -139,9 +139,9 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -35,7 +35,7 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr64sp }
# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' }
registers:
- { id: 0, class: gpr }
@ -132,12 +132,12 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr64 }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 4, class: gpr64 }
# CHECK-NEXT: - { id: 5, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -180,12 +180,12 @@ legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: fpr64 }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 4, class: gpr32 }
# CHECK-NEXT: - { id: 5, class: gpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: gpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -223,9 +223,9 @@ regBankSelected: true
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: fpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: fpr32 }
# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' }
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
@ -260,16 +260,16 @@ regBankSelected: true
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr32 }
# CHECK-NEXT: - { id: 1, class: gpr32 }
# CHECK-NEXT: - { id: 2, class: gpr32 }
# CHECK-NEXT: - { id: 3, class: gpr32 }
# CHECK-NEXT: - { id: 4, class: gpr64 }
# CHECK-NEXT: - { id: 5, class: gpr64 }
# CHECK-NEXT: - { id: 6, class: gpr64 }
# CHECK-NEXT: - { id: 7, class: gpr64 }
# CHECK-NEXT: - { id: 8, class: gpr64 }
# CHECK-NEXT: - { id: 9, class: gpr64 }
# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 5, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 6, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 7, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 8, class: gpr64, preferred-register: '' }
# CHECK-NEXT: - { id: 9, class: gpr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -4,7 +4,7 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
i32, ...) {
; CHECK-LABEL: name: test_varargs_sentinel
; CHECK: fixedStack:
; CHECK: - { id: [[VARARGS_SLOT:[0-9]+]], offset: 8
; CHECK: - { id: [[VARARGS_SLOT:[0-9]+]], type: default, offset: 8
; CHECK: body:
; CHECK: [[LIST:%[0-9]+]] = COPY %x0
; CHECK: [[VARARGS_AREA:%[0-9]+]] = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0

View File

@ -24,8 +24,8 @@ legalized: true
# CHECK-LABEL: name: load_constant
# CHECK: registers:
# CHECK: - { id: 0, class: sgpr }
# CHECK: - { id: 1, class: sgpr }
# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
body: |
bb.0:
@ -40,8 +40,8 @@ legalized: true
# CHECK-LABEL: name: load_global_uniform
# CHECK: registers:
# CHECK: - { id: 0, class: sgpr }
# CHECK: - { id: 1, class: sgpr }
# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
# CHECK: - { id: 1, class: sgpr, preferred-register: '' }
body: |
bb.0:
@ -56,9 +56,9 @@ legalized: true
# CHECK-LABEL: name: load_global_non_uniform
# CHECK: registers:
# CHECK: - { id: 0, class: sgpr }
# CHECK: - { id: 1, class: vgpr }
# CHECK: - { id: 2, class: vgpr }
# CHECK: - { id: 0, class: sgpr, preferred-register: '' }
# CHECK: - { id: 1, class: vgpr, preferred-register: '' }
# CHECK: - { id: 2, class: vgpr, preferred-register: '' }
body: |

View File

@ -2,13 +2,13 @@
# Check that coalescer does not create wider register tuple than in source
# CHECK: - { id: 2, class: vreg_64 }
# CHECK: - { id: 3, class: vreg_64 }
# CHECK: - { id: 4, class: vreg_64 }
# CHECK: - { id: 5, class: vreg_96 }
# CHECK: - { id: 6, class: vreg_96 }
# CHECK: - { id: 7, class: vreg_128 }
# CHECK: - { id: 8, class: vreg_128 }
# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
# No more registers shall be defined
# CHECK-NEXT: liveins:
# CHECK: FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %4,

View File

@ -802,8 +802,8 @@ fixedStack:
- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK-DAG: id: [[FI1:[0-9]+]], offset: 0
# CHECK-DAG: id: [[FI32:[0-9]+]], offset: 8
# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3

View File

@ -704,8 +704,8 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 60, size: 4
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
@ -757,7 +757,7 @@ declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
; CHECK-LABEL: name: test_fp_arrays_aapcs
; CHECK: fixedStack:
; CHECK: id: [[ARR2_ID:[0-9]+]], offset: 0, size: 8
; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[ARR0_0:%[0-9]+]](s32) = COPY %r0
; CHECK: [[ARR0_1:%[0-9]+]](s32) = COPY %r1
@ -817,10 +817,10 @@ declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3
define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
; CHECK-LABEL: name: test_fp_arrays_aapcs_vfp
; CHECK: fixedStack:
; CHECK-DAG: id: [[Z0_ID:[0-9]+]], offset: 0, size: 8
; CHECK-DAG: id: [[Z1_ID:[0-9]+]], offset: 8, size: 8
; CHECK-DAG: id: [[Z2_ID:[0-9]+]], offset: 16, size: 8
; CHECK-DAG: id: [[Z3_ID:[0-9]+]], offset: 24, size: 8
; CHECK-DAG: id: [[Z0_ID:[0-9]+]], type: default, offset: 0, size: 8,
; CHECK-DAG: id: [[Z1_ID:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
; CHECK: [[X0:%[0-9]+]](s64) = COPY %d0
; CHECK: [[X1:%[0-9]+]](s64) = COPY %d1
@ -918,8 +918,8 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], offset: 0, size: 4
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], offset: 76, size: 4
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
@ -981,8 +981,8 @@ declare arm_aapcscc {i32, i32} @structs_target({i32, i32}, {i32*, float, i32, do
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x, {i32*, float, i32, double} %y) {
; CHECK-LABEL: test_structs
; CHECK: fixedStack:
; CHECK-DAG: id: [[Y2_ID:[0-9]+]], offset: 0, size: 4
; CHECK-DAG: id: [[Y3_ID:[0-9]+]], offset: 8, size: 8
; CHECK-DAG: id: [[Y2_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[Y3_ID:[0-9]+]], type: default, offset: 8, size: 8,
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1

View File

@ -317,7 +317,7 @@ fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK: id: [[FRAME_INDEX:[0-9]+]], offset: 8
# CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
body: |
bb.0:
liveins: %r0, %r1, %r2, %r3

View File

@ -45,9 +45,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -71,12 +71,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -106,12 +106,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -141,12 +141,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -176,9 +176,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -202,12 +202,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -237,12 +237,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -272,9 +272,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -298,12 +298,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -333,12 +333,12 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -368,9 +368,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -394,9 +394,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -420,13 +420,13 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 6, class: fprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
# CHECK: - { id: 6, class: fprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -456,13 +456,13 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 5, class: gprb }
# CHECK: - { id: 6, class: fprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
# CHECK: - { id: 5, class: gprb, preferred-register: '' }
# CHECK: - { id: 6, class: fprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -498,11 +498,11 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -531,9 +531,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -556,7 +556,7 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
body: |
@ -572,8 +572,8 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -593,8 +593,8 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -614,8 +614,8 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -635,9 +635,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: fprb }
# CHECK: - { id: 1, class: fprb }
# CHECK: - { id: 2, class: fprb }
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -661,9 +661,9 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: fprb }
# CHECK: - { id: 1, class: fprb }
# CHECK: - { id: 2, class: fprb }
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -687,11 +687,11 @@ legalized: true
regBankSelected: false
selected: false
# CHECK: registers:
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: fprb }
# CHECK: - { id: 3, class: gprb }
# CHECK: - { id: 4, class: gprb }
# CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: fprb, preferred-register: '' }
# CHECK: - { id: 3, class: gprb, preferred-register: '' }
# CHECK: - { id: 4, class: gprb, preferred-register: '' }
registers:
- { id: 0, class: _ }

View File

@ -4,8 +4,8 @@
; this point. Notably, if it isn't is will be invalid and reference a
; deleted block (%bb.-1.if.end)
; CHECK-NOT: savePoint:
; CHECK-NOT: restorePoint:
; CHECK: savePoint: ''
; CHECK: restorePoint: ''
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7"

View File

@ -7,8 +7,8 @@
---
# CHECK-LABEL: name: func
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: fpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: fpr, preferred-register: '' }
name: func
body: |
bb.0:

View File

@ -25,7 +25,9 @@ frameInfo:
maxAlignment: 8
# CHECK-LABEL: stack_local
# CHECK: stack:
# CHECK-NEXT: { id: 0, name: local_var, offset: 0, size: 8, alignment: 8, local-offset: -8 }
# CHECK-NEXT: { id: 0, name: local_var, type: default, offset: 0, size: 8, alignment: 8,
# CHECK-NEXT: callee-saved-register: '', local-offset: -8, di-variable: '', di-expression: '',
# CHECK-NEXT: di-location: '' }
stack:
- { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 }
body: |

View File

@ -36,9 +36,13 @@ tracksRegLiveness: true
# CHECK-NEXT: maxAlignment:
# CHECK-NEXT: adjustsStack: false
# CHECK-NEXT: hasCalls: false
# CHECK-NEXT: stackProtector: ''
# CHECK-NEXT: maxCallFrameSize:
# CHECK-NEXT: hasOpaqueSPAdjustment: false
# CHECK-NEXT: hasVAStart: false
# CHECK-NEXT: hasMustTailInVarArgFunc: false
# CHECK-NEXT: savePoint: ''
# CHECK-NEXT: restorePoint: ''
# CHECK: body
frameInfo:
maxAlignment: 4
@ -61,6 +65,7 @@ tracksRegLiveness: true
# CHECK-NEXT: maxAlignment:
# CHECK-NEXT: adjustsStack: true
# CHECK-NEXT: hasCalls: true
# CHECK-NEXT: stackProtector: ''
# CHECK-NEXT: maxCallFrameSize: 4
# CHECK-NEXT: hasOpaqueSPAdjustment: true
# CHECK-NEXT: hasVAStart: true

View File

@ -50,12 +50,12 @@ frameInfo:
adjustsStack: true
hasCalls: true
# CHECK: fixedStack:
# CHECK-NEXT: , callee-saved-register: '%rbx' }
# CHECK: , callee-saved-register: '%rbx' }
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
# CHECK: stack:
# CHECK-NEXT: - { id: 0
# CHECK-NEXT: , callee-saved-register: '%edi' }
# CHECK: callee-saved-register: '%edi'
stack:
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }

View File

@ -20,7 +20,7 @@ frameInfo:
stackSize: 4
maxAlignment: 4
# CHECK: fixedStack:
# CHECK-NEXT: - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK-NEXT: - { id: 0, type: default, offset: 0, size: 4, alignment: 4, isImmutable: true,
fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
stack:

View File

@ -19,11 +19,11 @@
---
name: test_vregs
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
# CHECK-NEXT: - { id: 2, class: _ }
# CHECK-NEXT: - { id: 3, class: _ }
# CHECK-NEXT: - { id: 4, class: _ }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -1,4 +1,4 @@
# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
# Test various aspects of register class specification on machine operands.
--- |
define void @func() { ret void }
@ -6,11 +6,11 @@
---
# CHECK-LABEL: name: func
# CHECK: registers:
# CHECK: - { id: 0, class: gr32 }
# CHECK: - { id: 1, class: gr64 }
# CHECK: - { id: 2, class: gr32 }
# CHECK: - { id: 3, class: gr16 }
# CHECK: - { id: 4, class: _ }
# CHECK: - { id: 0, class: gr32, preferred-register: '' }
# CHECK: - { id: 1, class: gr64, preferred-register: '' }
# CHECK: - { id: 2, class: gr32, preferred-register: '' }
# CHECK: - { id: 3, class: gr16, preferred-register: '' }
# CHECK: - { id: 4, class: _, preferred-register: '' }
name: func
body: |
bb.0:

View File

@ -15,7 +15,7 @@
name: test
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '%esi' }
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '%edi' }
registers:

View File

@ -19,7 +19,7 @@ name: test
frameInfo:
maxAlignment: 4
# CHECK: fixedStack:
# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' }
fixedStack:
- { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
stack:

View File

@ -51,8 +51,9 @@ frameInfo:
maxAlignment: 16
# CHECK-LABEL: foo
# CHECK: stack:
# CHECK: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
# CHECK-NEXT: di-expression: '!10', di-location: '!11' }
# CHECK: - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16,
# CHECK-NEXT: callee-saved-register: '', di-variable: '!4', di-expression: '!10',
# CHECK-NEXT: di-location: '!11' }
stack:
- { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
di-expression: '!7', di-location: '!8' }

View File

@ -21,9 +21,12 @@ name: test
frameInfo:
maxAlignment: 8
# CHECK: stack:
# CHECK-NEXT: - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
# CHECK-NEXT: - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
# CHECK-NEXT: - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
# CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
# CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
stack:
- { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
- { id: 1, name: x, offset: -24, size: 8, alignment: 8 }

View File

@ -24,9 +24,11 @@ frameInfo:
maxAlignment: 8
adjustsStack: true
# CHECK: stack:
# CHECK-NEXT: - { id: 0, offset: -20, size: 4, alignment: 4 }
# CHECK-NEXT: - { id: 1, offset: -32, size: 8, alignment: 8 }
# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
# CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
stack:
- { id: 0, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -32, size: 8, alignment: 8 }

View File

@ -33,9 +33,9 @@
name: bar
tracksRegLiveness: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
@ -67,9 +67,9 @@ name: foo
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 2, class: gr32 }
- { id: 0, class: gr32 }

View File

@ -11,8 +11,8 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
; ALL-LABEL: name: test_i8_args_8
; X64: fixedStack:
; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false
; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false
; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
; X64: [[ARG1:%[0-9]+]](s8) = COPY %edi
; X64-NEXT: %{{[0-9]+}}(s8) = COPY %esi
@ -26,14 +26,14 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 1, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 1, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 1, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 1, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 1, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 1, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 1, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4, isImmutable: true,
; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 1, alignment: 8, isImmutable: true,
; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 1, alignment: 4, isImmutable: true,
; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 1, alignment: 16, isImmutable: true,
; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 1, alignment: 4, isImmutable: true,
; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 1, alignment: 8, isImmutable: true,
; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 1, alignment: 4, isImmutable: true,
; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, isImmutable: true,
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@ -77,8 +77,8 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
; ALL-LABEL: name: test_i32_args_8
; X64: fixedStack:
; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false
; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false
; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
; X64: [[ARG1:%[0-9]+]](s32) = COPY %edi
; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi
@ -92,14 +92,14 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@ -142,8 +142,8 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
; ALL-LABEL: name: test_i64_args_8
; X64: fixedStack:
; X64: id: [[STACK8:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false
; X64: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false
; X64: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
; X64: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9
; X64: [[ARG1:%[0-9]+]](s64) = COPY %rdi
; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi
@ -157,22 +157,22 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
; X32: fixedStack:
; X32: id: [[STACK60:[0-9]+]], offset: 60, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK56:[0-9]+]], offset: 56, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK52:[0-9]+]], offset: 52, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK48:[0-9]+]], offset: 48, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK44:[0-9]+]], offset: 44, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK40:[0-9]+]], offset: 40, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK36:[0-9]+]], offset: 36, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK32:[0-9]+]], offset: 32, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK28:[0-9]+]], offset: 28, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK24:[0-9]+]], offset: 24, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK20:[0-9]+]], offset: 20, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK16:[0-9]+]], offset: 16, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK12:[0-9]+]], offset: 12, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK8:[0-9]+]], offset: 8, size: 4, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK56:[0-9]+]], type: default, offset: 56, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK52:[0-9]+]], type: default, offset: 52, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK48:[0-9]+]], type: default, offset: 48, size: 4, alignment: 16, isImmutable: true,
; X32: id: [[STACK44:[0-9]+]], type: default, offset: 44, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK40:[0-9]+]], type: default, offset: 40, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK36:[0-9]+]], type: default, offset: 36, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK32:[0-9]+]], type: default, offset: 32, size: 4, alignment: 16, isImmutable: true,
; X32: id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK24:[0-9]+]], type: default, offset: 24, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK20:[0-9]+]], type: default, offset: 20, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 4, alignment: 16, isImmutable: true,
; X32: id: [[STACK12:[0-9]+]], type: default, offset: 12, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 4, alignment: 8, isImmutable: true,
; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
; X32: [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
@ -249,8 +249,8 @@ define float @test_float_args(float %arg1, float %arg2) {
; X64-NEXT: RET 0, implicit %xmm0
; X32: fixedStack:
; X32: id: [[STACK4:[0-9]+]], offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK4:[0-9]+]], type: default, offset: 4, size: 4, alignment: 4, isImmutable: true,
; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@ -270,8 +270,8 @@ define double @test_double_args(double %arg1, double %arg2) {
; X64-NEXT: RET 0, implicit %xmm0
; X32: fixedStack:
; X32: id: [[STACK4:[0-9]+]], offset: 8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
; X32: id: [[STACK0:[0-9]+]], offset: 0, size: 8, alignment: 16, isImmutable: true, isAliased: false }
; X32: id: [[STACK4:[0-9]+]], type: default, offset: 8, size: 8, alignment: 8, isImmutable: true,
; X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16, isImmutable: true,
; X32: [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
; X32-NEXT: [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
@ -322,7 +322,7 @@ define i32 * @test_memop_i32(i32 * %p1) {
;X64-NEXT: RET 0, implicit %rax
;X32: fixedStack:
;X32: id: [[STACK0:[0-9]+]], offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
;X32: id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16, isImmutable: true,
;X32: %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
;X32-NEXT: %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
;X32-NEXT: %eax = COPY %0(p0)

View File

@ -24,9 +24,9 @@ alignment: 4
legalized: false
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
# CHECK-NEXT: - { id: 2, class: _ }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -56,9 +56,9 @@ alignment: 4
legalized: false
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
# CHECK-NEXT: - { id: 2, class: _ }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -88,9 +88,9 @@ alignment: 4
legalized: false
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: _ }
# CHECK-NEXT: - { id: 1, class: _ }
# CHECK-NEXT: - { id: 2, class: _ }
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -26,9 +26,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -56,9 +56,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -86,9 +86,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -26,9 +26,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -56,9 +56,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -86,9 +86,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -28,9 +28,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -58,9 +58,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -88,9 +88,9 @@ alignment: 4
legalized: false
regBankSelected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: _ }
# ALL-NEXT: - { id: 1, class: _ }
# ALL-NEXT: - { id: 2, class: _ }
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -33,8 +33,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_mul_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -56,8 +56,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -79,8 +79,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_sub_vec256
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -100,8 +100,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: vecr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -122,8 +122,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -33,8 +33,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr }
# CHECK-NEXT: - { id: 1, class: vecr }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -53,8 +53,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr }
# CHECK-NEXT: - { id: 1, class: vecr }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -73,8 +73,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr }
# CHECK-NEXT: - { id: 1, class: vecr }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -93,8 +93,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: vecr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -115,8 +115,8 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vecr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -14,11 +14,11 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 4, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -145,9 +145,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_i8
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -172,9 +172,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_i16
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -199,9 +199,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_i32
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -226,9 +226,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_i64
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 2, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -253,14 +253,14 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_mul_gpr
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 2, class: gpr }
# CHECK: - { id: 3, class: gpr }
# CHECK: - { id: 4, class: gpr }
# CHECK: - { id: 5, class: gpr }
# CHECK: - { id: 6, class: gpr }
# CHECK: - { id: 7, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
# CHECK: - { id: 2, class: gpr, preferred-register: '' }
# CHECK: - { id: 3, class: gpr, preferred-register: '' }
# CHECK: - { id: 4, class: gpr, preferred-register: '' }
# CHECK: - { id: 5, class: gpr, preferred-register: '' }
# CHECK: - { id: 6, class: gpr, preferred-register: '' }
# CHECK: - { id: 7, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -292,9 +292,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_float
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 2, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -319,9 +319,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_double
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 2, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -346,9 +346,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_v4i32
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 2, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -373,9 +373,9 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_v4f32
# CHECK: registers:
# CHECK: - { id: 0, class: vecr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 2, class: vecr }
# CHECK: - { id: 0, class: vecr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
# CHECK: - { id: 2, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -399,8 +399,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_i8
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -422,8 +422,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_i16
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -445,8 +445,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_i32
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -469,8 +469,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_i64
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -492,8 +492,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_float
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -515,8 +515,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_double
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -538,8 +538,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_load_v4i32
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: vecr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: vecr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -561,8 +561,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_store_i32
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -585,8 +585,8 @@ regBankSelected: false
selected: false
# CHECK-LABEL: name: test_store_i64
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
# CHECK: - { id: 0, class: gpr, preferred-register: '' }
# CHECK: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -610,12 +610,12 @@ selected: false
# CHECK-LABEL: name: test_store_float
# CHECK: registers:
# FAST-NEXT: - { id: 0, class: vecr }
# FAST-NEXT: - { id: 1, class: gpr }
# FAST-NEXT: - { id: 2, class: gpr }
# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 0, class: vecr }
# GREEDY-NEXT: - { id: 1, class: gpr }
# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -647,12 +647,12 @@ selected: false
# CHECK-LABEL: name: test_store_double
# CHECK: registers:
# FAST-NEXT: - { id: 0, class: vecr }
# FAST-NEXT: - { id: 1, class: gpr }
# FAST-NEXT: - { id: 2, class: gpr }
# FAST-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# FAST-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# FAST-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# GREEDY-NEXT: - { id: 0, class: vecr }
# GREEDY-NEXT: - { id: 1, class: gpr }
# GREEDY-NEXT: - { id: 0, class: vecr, preferred-register: '' }
# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
@ -682,10 +682,10 @@ alignment: 4
legalized: true
# CHECK-LABEL: name: constInt_check
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -706,10 +706,10 @@ alignment: 4
legalized: true
# CHECK-LABEL: name: trunc_check
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -729,11 +729,11 @@ name: test_gep
legalized: true
# CHECK-LABEL: name: test_gep
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 3, class: gpr }
# CHECK-NEXT: - { id: 4, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -757,9 +757,9 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -782,9 +782,9 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -807,9 +807,9 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@ -832,9 +832,9 @@ alignment: 4
legalized: true
regBankSelected: false
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr }
# CHECK-NEXT: - { id: 1, class: gpr }
# CHECK-NEXT: - { id: 2, class: gpr }
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }

View File

@ -32,19 +32,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128 }
# AVX512VL-NEXT: - { id: 1, class: vr128 }
# AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -74,19 +74,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128 }
# AVX512VL-NEXT: - { id: 1, class: vr128 }
# AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -116,19 +116,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -158,19 +158,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -30,19 +30,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256 }
# AVX512VL-NEXT: - { id: 1, class: vr256 }
# AVX512VL-NEXT: - { id: 2, class: vr256 }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -70,19 +70,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256 }
# AVX512VL-NEXT: - { id: 1, class: vr256 }
# AVX512VL-NEXT: - { id: 2, class: vr256 }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -110,19 +110,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x }
# AVX512VL-NEXT: - { id: 1, class: vr256x }
# AVX512VL-NEXT: - { id: 2, class: vr256x }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -150,19 +150,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x }
# AVX512VL-NEXT: - { id: 1, class: vr256x }
# AVX512VL-NEXT: - { id: 2, class: vr256x }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -31,9 +31,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -57,9 +57,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -83,9 +83,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -109,9 +109,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -13,16 +13,16 @@ alignment: 4
legalized: true
regBankSelected: true
# X32: registers:
# X32-NEXT: - { id: 0, class: gr32 }
# X32-NEXT: - { id: 1, class: gr32 }
# X32-NEXT: - { id: 2, class: gr32 }
# X32-NEXT: - { id: 3, class: gr32 }
# X32-NEXT: - { id: 4, class: gpr }
# X32-NEXT: - { id: 5, class: gr32 }
# X32-NEXT: - { id: 6, class: gr32 }
# X32-NEXT: - { id: 7, class: gr32 }
# X32-NEXT: - { id: 8, class: gr32 }
# X32-NEXT: - { id: 9, class: gpr }
# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 4, class: gpr, preferred-register: '' }
# X32-NEXT: - { id: 5, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 6, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 7, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 8, class: gr32, preferred-register: '' }
# X32-NEXT: - { id: 9, class: gpr, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -51,9 +51,9 @@ name: test_add_i64
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr64 }
# ALL-NEXT: - { id: 1, class: gr64 }
# ALL-NEXT: - { id: 2, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -78,9 +78,9 @@ name: test_add_i32
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -106,9 +106,9 @@ legalized: true
regBankSelected: true
selected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr16 }
# ALL-NEXT: - { id: 2, class: gr16 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -135,9 +135,9 @@ legalized: true
regBankSelected: true
selected: false
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr8 }
# ALL-NEXT: - { id: 2, class: gr8 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -165,12 +165,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr32 }
# NO_AVX512F-NEXT: - { id: 1, class: fr32 }
# NO_AVX512F-NEXT: - { id: 2, class: fr32 }
# AVX512ALL-NEXT: - { id: 0, class: fr32x }
# AVX512ALL-NEXT: - { id: 1, class: fr32x }
# AVX512ALL-NEXT: - { id: 2, class: fr32x }
# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -200,12 +200,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr64 }
# NO_AVX512F-NEXT: - { id: 1, class: fr64 }
# NO_AVX512F-NEXT: - { id: 2, class: fr64 }
# AVX512ALL-NEXT: - { id: 0, class: fr64x }
# AVX512ALL-NEXT: - { id: 1, class: fr64x }
# AVX512ALL-NEXT: - { id: 2, class: fr64x }
# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -235,12 +235,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -271,12 +271,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -87,11 +87,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr8 }
# CHECK-NEXT: - { id: 1, class: gr8 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -124,11 +124,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr16 }
# CHECK-NEXT: - { id: 1, class: gr16 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -161,11 +161,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 1, class: gr64 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -198,11 +198,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -235,11 +235,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -272,11 +272,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -309,11 +309,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -346,11 +346,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -383,11 +383,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -420,11 +420,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -457,11 +457,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -494,11 +494,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -531,11 +531,11 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 2, class: gr8 }
# CHECK-NEXT: - { id: 3, class: gr32 }
# CHECK-NEXT: - { id: 4, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr8, preferred-register: '' }
# CHECK-NEXT: - { id: 3, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 4, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -33,7 +33,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i8
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr8 }
# CHECK-NEXT: - { id: 0, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -52,7 +52,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i16
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr16 }
# CHECK-NEXT: - { id: 0, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -71,7 +71,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i32
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -90,7 +90,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i64
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -110,7 +110,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i64_u32
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -129,7 +129,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i64_i32
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:

View File

@ -25,10 +25,10 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr8 }
# ALL-NEXT: - { id: 2, class: gr64 }
# ALL-NEXT: - { id: 3, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -57,8 +57,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -83,8 +83,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -35,9 +35,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -63,8 +63,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -89,8 +89,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -115,8 +115,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -141,8 +141,8 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -14,9 +14,9 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: test_gep_i32
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 1, class: gr64_nosp }
# CHECK-NEXT: - { id: 2, class: gr64 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -13,10 +13,10 @@ name: test_add_i8
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# INC-NEXT: - { id: 1, class: gpr }
# ADD-NEXT: - { id: 1, class: gr8 }
# ALL-NEXT: - { id: 2, class: gr8 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' }
# ADD-NEXT: - { id: 1, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -29,7 +29,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i32_1
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -47,7 +47,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i32_1_optsize
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -65,7 +65,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i32_1b
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:
@ -83,7 +83,7 @@ regBankSelected: true
selected: false
# CHECK-LABEL: name: const_i32_1_optsizeb
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
# CHECK: body:

View File

@ -49,9 +49,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr8 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -79,9 +79,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr16 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -109,9 +109,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -139,10 +139,10 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr8 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 3, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -176,10 +176,10 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 3, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -213,10 +213,10 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 3, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -250,9 +250,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -280,10 +280,10 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 3, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 3, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -91,8 +91,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr8 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr8, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -115,8 +115,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr16 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr16, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -139,8 +139,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr32 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -163,8 +163,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -187,8 +187,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr32 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -211,9 +211,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: fr32 }
# AVX512ALL: - { id: 1, class: fr32x }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F: - { id: 1, class: fr32, preferred-register: '' }
# AVX512ALL: - { id: 1, class: fr32x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
@ -238,8 +238,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -262,9 +262,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: fr64 }
# AVX512ALL: - { id: 1, class: fr64x }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F: - { id: 1, class: fr64, preferred-register: '' }
# AVX512ALL: - { id: 1, class: fr64x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
@ -289,8 +289,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr32 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr32, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %edi
@ -315,8 +315,8 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %rdi
@ -341,9 +341,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: fr32x }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 2, class: gr32 }
# ALL: - { id: 0, class: fr32x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
# ALL: - { id: 2, class: gr32, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
@ -371,9 +371,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: fr32 }
# AVX512ALL: - { id: 0, class: fr32x }
# ALL: - { id: 1, class: gr64 }
# NO_AVX512F: - { id: 0, class: fr32, preferred-register: '' }
# AVX512ALL: - { id: 0, class: fr32x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
@ -400,9 +400,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: fr64x }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 2, class: gr64 }
# ALL: - { id: 0, class: fr64x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
# ALL: - { id: 2, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
@ -430,9 +430,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: fr64 }
# AVX512ALL: - { id: 0, class: fr64x }
# ALL: - { id: 1, class: gr64 }
# NO_AVX512F: - { id: 0, class: fr64, preferred-register: '' }
# AVX512ALL: - { id: 0, class: fr64x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
@ -460,8 +460,8 @@ legalized: true
regBankSelected: true
selected: false
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
@ -483,8 +483,8 @@ legalized: true
regBankSelected: true
selected: false
registers:
# ALL: - { id: 0, class: gr64 }
# ALL: - { id: 1, class: gr64 }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: gpr }
# ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1)

View File

@ -32,9 +32,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
@ -60,9 +60,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# ALL: - { id: 0, class: gr64 }
# NO_AVX512F: - { id: 1, class: vr128 }
# AVX512ALL: - { id: 1, class: vr128x }
# ALL: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F: - { id: 1, class: vr128, preferred-register: '' }
# AVX512ALL: - { id: 1, class: vr128x, preferred-register: '' }
- { id: 0, class: gpr }
- { id: 1, class: vecr }
# ALL: %0 = COPY %rdi
@ -88,9 +88,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0
@ -118,9 +118,9 @@ alignment: 4
legalized: true
regBankSelected: true
registers:
# NO_AVX512F: - { id: 0, class: vr128 }
# AVX512ALL: - { id: 0, class: vr128x }
# ALL: - { id: 1, class: gr64 }
# NO_AVX512F: - { id: 0, class: vr128, preferred-register: '' }
# AVX512ALL: - { id: 0, class: vr128x, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: vecr }
- { id: 1, class: gpr }
# ALL: %0 = COPY %xmm0

View File

@ -33,12 +33,12 @@ alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: gr64 }
# NO_AVX512F-NEXT: - { id: 1, class: vr256 }
# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: gr64 }
# AVX512ALL-NEXT: - { id: 1, class: vr256x }
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@ -73,12 +73,12 @@ alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: gr64 }
# NO_AVX512F-NEXT: - { id: 1, class: vr256 }
# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: gr64 }
# AVX512ALL-NEXT: - { id: 1, class: vr256x }
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@ -113,12 +113,12 @@ alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: vr256 }
# NO_AVX512F-NEXT: - { id: 1, class: gr64 }
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x }
# AVX512ALL-NEXT: - { id: 1, class: gr64 }
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
@ -153,12 +153,12 @@ alignment: 4
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
# NO_AVX512F-NEXT: - { id: 0, class: vr256 }
# NO_AVX512F-NEXT: - { id: 1, class: gr64 }
# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
#
# AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x }
# AVX512ALL-NEXT: - { id: 1, class: gr64 }
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }

View File

@ -28,8 +28,8 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX512F: registers:
# AVX512F-NEXT: - { id: 0, class: gr64 }
# AVX512F-NEXT: - { id: 1, class: vr512 }
# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@ -54,8 +54,8 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX512F: registers:
# AVX512F-NEXT: - { id: 0, class: gr64 }
# AVX512F-NEXT: - { id: 1, class: vr512 }
# AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512F-NEXT: - { id: 1, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@ -80,8 +80,8 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX512F: registers:
# AVX512F-NEXT: - { id: 0, class: vr512 }
# AVX512F-NEXT: - { id: 1, class: gr64 }
# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
@ -106,8 +106,8 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX512F: registers:
# AVX512F-NEXT: - { id: 0, class: vr512 }
# AVX512F-NEXT: - { id: 1, class: gr64 }
# AVX512F-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }

View File

@ -24,9 +24,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr16 }
# ALL-NEXT: - { id: 1, class: gr16 }
# ALL-NEXT: - { id: 2, class: gr16 }
# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -55,9 +55,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -86,9 +86,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr64 }
# ALL-NEXT: - { id: 1, class: gr64 }
# ALL-NEXT: - { id: 2, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -95,9 +95,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128 }
# CHECK-NEXT: - { id: 1, class: vr128 }
# CHECK-NEXT: - { id: 2, class: vr128 }
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -121,9 +121,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128 }
# CHECK-NEXT: - { id: 1, class: vr128 }
# CHECK-NEXT: - { id: 2, class: vr128 }
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -147,9 +147,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128x }
# CHECK-NEXT: - { id: 1, class: vr128x }
# CHECK-NEXT: - { id: 2, class: vr128x }
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -173,9 +173,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128 }
# CHECK-NEXT: - { id: 1, class: vr128 }
# CHECK-NEXT: - { id: 2, class: vr128 }
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -199,9 +199,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128 }
# CHECK-NEXT: - { id: 1, class: vr128 }
# CHECK-NEXT: - { id: 2, class: vr128 }
# CHECK-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -225,9 +225,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128x }
# CHECK-NEXT: - { id: 1, class: vr128x }
# CHECK-NEXT: - { id: 2, class: vr128x }
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -251,9 +251,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr128x }
# CHECK-NEXT: - { id: 1, class: vr128x }
# CHECK-NEXT: - { id: 2, class: vr128x }
# CHECK-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -277,9 +277,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr256 }
# CHECK-NEXT: - { id: 1, class: vr256 }
# CHECK-NEXT: - { id: 2, class: vr256 }
# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -303,9 +303,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr256x }
# CHECK-NEXT: - { id: 1, class: vr256x }
# CHECK-NEXT: - { id: 2, class: vr256x }
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -329,9 +329,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr256 }
# CHECK-NEXT: - { id: 1, class: vr256 }
# CHECK-NEXT: - { id: 2, class: vr256 }
# CHECK-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr256, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -355,9 +355,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr256x }
# CHECK-NEXT: - { id: 1, class: vr256x }
# CHECK-NEXT: - { id: 2, class: vr256x }
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -381,9 +381,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr256x }
# CHECK-NEXT: - { id: 1, class: vr256x }
# CHECK-NEXT: - { id: 2, class: vr256x }
# CHECK-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -407,9 +407,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr512 }
# CHECK-NEXT: - { id: 1, class: vr512 }
# CHECK-NEXT: - { id: 2, class: vr512 }
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -433,9 +433,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr512 }
# CHECK-NEXT: - { id: 1, class: vr512 }
# CHECK-NEXT: - { id: 2, class: vr512 }
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -459,9 +459,9 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: vr512 }
# CHECK-NEXT: - { id: 1, class: vr512 }
# CHECK-NEXT: - { id: 2, class: vr512 }
# CHECK-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# CHECK-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -32,19 +32,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128 }
# AVX512VL-NEXT: - { id: 1, class: vr128 }
# AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -74,19 +74,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128 }
# AVX512VL-NEXT: - { id: 1, class: vr128 }
# AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -116,19 +116,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -158,19 +158,19 @@ alignment: 4
legalized: true
regBankSelected: true
# NOVL: registers:
# NOVL-NEXT: - { id: 0, class: vr128 }
# NOVL-NEXT: - { id: 1, class: vr128 }
# NOVL-NEXT: - { id: 2, class: vr128 }
# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr128x }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x }
# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -30,19 +30,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256 }
# AVX512VL-NEXT: - { id: 1, class: vr256 }
# AVX512VL-NEXT: - { id: 2, class: vr256 }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -70,19 +70,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256 }
# AVX512VL-NEXT: - { id: 1, class: vr256 }
# AVX512VL-NEXT: - { id: 2, class: vr256 }
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -110,19 +110,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x }
# AVX512VL-NEXT: - { id: 1, class: vr256x }
# AVX512VL-NEXT: - { id: 2, class: vr256x }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -150,19 +150,19 @@ alignment: 4
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256 }
# AVX2-NEXT: - { id: 1, class: vr256 }
# AVX2-NEXT: - { id: 2, class: vr256 }
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x }
# AVX512VL-NEXT: - { id: 1, class: vr256x }
# AVX512VL-NEXT: - { id: 2, class: vr256x }
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x }
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -31,9 +31,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -57,9 +57,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -83,9 +83,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -109,9 +109,9 @@ alignment: 4
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: vr512 }
# ALL-NEXT: - { id: 1, class: vr512 }
# ALL-NEXT: - { id: 2, class: vr512 }
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: vr512, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -40,9 +40,9 @@ name: test_sub_i64
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr64 }
# ALL-NEXT: - { id: 1, class: gr64 }
# ALL-NEXT: - { id: 2, class: gr64 }
# ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr64, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -66,9 +66,9 @@ name: test_sub_i32
legalized: true
regBankSelected: true
# ALL: registers:
# ALL-NEXT: - { id: 0, class: gr32 }
# ALL-NEXT: - { id: 1, class: gr32 }
# ALL-NEXT: - { id: 2, class: gr32 }
# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -94,12 +94,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr32 }
# NO_AVX512F-NEXT: - { id: 1, class: fr32 }
# NO_AVX512F-NEXT: - { id: 2, class: fr32 }
# AVX512ALL-NEXT: - { id: 0, class: fr32x }
# AVX512ALL-NEXT: - { id: 1, class: fr32x }
# AVX512ALL-NEXT: - { id: 2, class: fr32x }
# NO_AVX512F-NEXT: - { id: 0, class: fr32, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: fr32, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: fr32, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: fr32x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: fr32x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: fr32x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -128,12 +128,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512F-NEXT: - { id: 0, class: fr64 }
# NO_AVX512F-NEXT: - { id: 1, class: fr64 }
# NO_AVX512F-NEXT: - { id: 2, class: fr64 }
# AVX512ALL-NEXT: - { id: 0, class: fr64x }
# AVX512ALL-NEXT: - { id: 1, class: fr64x }
# AVX512ALL-NEXT: - { id: 2, class: fr64x }
# NO_AVX512F-NEXT: - { id: 0, class: fr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 1, class: fr64, preferred-register: '' }
# NO_AVX512F-NEXT: - { id: 2, class: fr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 0, class: fr64x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: fr64x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 2, class: fr64x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -161,12 +161,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@ -196,12 +196,12 @@ regBankSelected: true
selected: false
tracksRegLiveness: true
# ALL: registers:
# NO_AVX512VL-NEXT: - { id: 0, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128 }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128 }
# AVX512VL-NEXT: - { id: 0, class: vr128x }
# AVX512VL-NEXT: - { id: 1, class: vr128x }
# AVX512VL-NEXT: - { id: 2, class: vr128x }
# NO_AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
# NO_AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }

View File

@ -38,8 +38,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr8 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -64,8 +64,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr8 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -90,8 +90,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr32 }
# CHECK-NEXT: - { id: 1, class: gr16 }
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -116,8 +116,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit }
# CHECK-NEXT: - { id: 1, class: gr8 }
# CHECK-NEXT: - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr8, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -142,8 +142,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 1, class: gr16 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr16, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
@ -168,8 +168,8 @@ alignment: 4
legalized: true
regBankSelected: true
# CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gr64 }
# CHECK-NEXT: - { id: 1, class: gr32 }
# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }

View File

@ -15,5 +15,5 @@ body:
; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
; POST-RA: liveins:
; POST-RA-NEXT: - { reg: '%edi' }
; POST-RA-NEXT: - { reg: '%esi' }
; POST-RA-NEXT: - { reg: '%edi', virtual-reg: '' }
; POST-RA-NEXT: - { reg: '%esi', virtual-reg: '' }