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[SCEV] Improve the run-time checking of the NoWrap predicate
Summary:
This implements a new method of run-time checking the NoWrap
SCEV predicates, which should be easier to optimize and nicer
for targets that don't correctly handle multiplication/addition
of large integer types (like i128).
If the AddRec is {a,+,b} and the backedge taken count is c,
the idea is to check that |b| * c doesn't have unsigned overflow,
and depending on the sign of b, that:
a + |b| * c >= a (b >= 0) or
a - |b| * c <= a (b <= 0)
where the comparisons above are signed or unsigned, depending on
the flag that we're checking.
The advantage of doing this is that we avoid extending to a larger
type and we avoid the multiplication of large types (multiplying
i128 can be expensive).
Reviewers: sanjoy
Subscribers: llvm-commits, mzolotukhin
Differential Revision: http://reviews.llvm.org/D19266
llvm-svn: 267389
This commit is contained in:
Silviu Baranga
parent
5a59940bb3
commit
9d55b40815
@ -2007,37 +2007,81 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR,
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SCEVUnionPredicate Pred;
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const SCEV *ExitCount =
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SE.getPredicatedBackedgeTakenCount(AR->getLoop(), Pred);
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const SCEV *Step = AR->getStepRecurrence(SE);
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const SCEV *Start = AR->getStart();
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unsigned DstBits = SE.getTypeSizeInBits(AR->getType());
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unsigned SrcBits = SE.getTypeSizeInBits(ExitCount->getType());
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unsigned MaxBits = 2 * std::max(DstBits, SrcBits);
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auto *TripCount = SE.getTruncateOrZeroExtend(ExitCount, AR->getType());
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IntegerType *MaxTy = IntegerType::get(Loc->getContext(), MaxBits);
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assert(ExitCount != SE.getCouldNotCompute() && "Invalid loop count");
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const auto *ExtendedTripCount = SE.getZeroExtendExpr(ExitCount, MaxTy);
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const auto *ExtendedStep = SE.getSignExtendExpr(Step, MaxTy);
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const auto *ExtendedStart = Signed ? SE.getSignExtendExpr(Start, MaxTy)
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: SE.getZeroExtendExpr(Start, MaxTy);
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const SCEV *Step = AR->getStepRecurrence(SE);
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const SCEV *Start = AR->getStart();
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const SCEV *End = SE.getAddExpr(Start, SE.getMulExpr(TripCount, Step));
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const SCEV *RHS = Signed ? SE.getSignExtendExpr(End, MaxTy)
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: SE.getZeroExtendExpr(End, MaxTy);
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unsigned SrcBits = SE.getTypeSizeInBits(ExitCount->getType());
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unsigned DstBits = SE.getTypeSizeInBits(AR->getType());
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const SCEV *LHS = SE.getAddExpr(
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ExtendedStart, SE.getMulExpr(ExtendedTripCount, ExtendedStep));
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// The expression {Start,+,Step} has nusw/nssw if
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// Step < 0, Start - |Step| * Backedge <= Start
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// Step >= 0, Start + |Step| * Backedge > Start
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// and |Step| * Backedge doesn't unsigned overflow.
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// Do all SCEV expansions now.
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Value *LHSVal = expandCodeFor(LHS, MaxTy, Loc);
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Value *RHSVal = expandCodeFor(RHS, MaxTy, Loc);
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IntegerType *CountTy = IntegerType::get(Loc->getContext(), SrcBits);
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Builder.SetInsertPoint(Loc);
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Value *TripCountVal = expandCodeFor(ExitCount, CountTy, Loc);
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IntegerType *Ty =
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IntegerType::get(Loc->getContext(), SE.getTypeSizeInBits(AR->getType()));
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Value *StepValue = expandCodeFor(Step, Ty, Loc);
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Value *NegStepValue = expandCodeFor(SE.getNegativeSCEV(Step), Ty, Loc);
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Value *StartValue = expandCodeFor(Start, Ty, Loc);
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ConstantInt *Zero =
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ConstantInt::get(Loc->getContext(), APInt::getNullValue(DstBits));
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Builder.SetInsertPoint(Loc);
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// Compute |Step|
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Value *StepCompare = Builder.CreateICmp(ICmpInst::ICMP_SLT, StepValue, Zero);
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Value *AbsStep = Builder.CreateSelect(StepCompare, NegStepValue, StepValue);
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return Builder.CreateICmp(ICmpInst::ICMP_NE, RHSVal, LHSVal);
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// Get the backedge taken count and truncate or extended to the AR type.
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Value *TruncTripCount = Builder.CreateZExtOrTrunc(TripCountVal, Ty);
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auto *MulF = Intrinsic::getDeclaration(Loc->getModule(),
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Intrinsic::umul_with_overflow, Ty);
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// Compute |Step| * Backedge
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CallInst *Mul = Builder.CreateCall(MulF, {AbsStep, TruncTripCount}, "mul");
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Value *MulV = Builder.CreateExtractValue(Mul, 0, "mul.result");
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Value *OfMul = Builder.CreateExtractValue(Mul, 1, "mul.overflow");
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// Compute:
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// Start + |Step| * Backedge < Start
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// Start - |Step| * Backedge > Start
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Value *Add = Builder.CreateAdd(StartValue, MulV);
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Value *Sub = Builder.CreateSub(StartValue, MulV);
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Value *EndCompareGT = Builder.CreateICmp(
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Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT, Sub, StartValue);
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Value *EndCompareLT = Builder.CreateICmp(
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Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, Add, StartValue);
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// Select the answer based on the sign of Step.
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Value *EndCheck =
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Builder.CreateSelect(StepCompare, EndCompareGT, EndCompareLT);
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// If the backedge taken count type is larger than the AR type,
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// check that we don't drop any bits by truncating it. If we are
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// droping bits, then we have overflow (unless the step is zero).
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if (SE.getTypeSizeInBits(CountTy) > SE.getTypeSizeInBits(Ty)) {
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auto MaxVal = APInt::getMaxValue(DstBits).zext(SrcBits);
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auto *BackedgeCheck =
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Builder.CreateICmp(ICmpInst::ICMP_UGT, TripCountVal,
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ConstantInt::get(Loc->getContext(), MaxVal));
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BackedgeCheck = Builder.CreateAnd(
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BackedgeCheck, Builder.CreateICmp(ICmpInst::ICMP_NE, StepValue, Zero));
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EndCheck = Builder.CreateOr(EndCheck, BackedgeCheck);
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}
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EndCheck = Builder.CreateOr(EndCheck, OfMul);
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return EndCheck;
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}
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Value *SCEVExpander::expandWrapPredicate(const SCEVWrapPredicate *Pred,
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@ -38,9 +38,32 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; LV-LABEL: f1
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; LV-LABEL: for.body.lver.check
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; LV: [[PredCheck0:%[^ ]*]] = icmp ne i128
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; LV: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[PredCheck1:%[^ ]*]] = icmp ne i128
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; LV: [[BETrunc:%[^ ]*]] = trunc i64 [[BE:%[^ ]*]] to i32
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; LV-NEXT: [[OFMul:%[^ ]*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[BETrunc]])
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; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 0
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; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 1
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; LV-NEXT: [[AddEnd:%[^ ]*]] = add i32 0, [[OFMulResult]]
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; LV-NEXT: [[SubEnd:%[^ ]*]] = sub i32 0, [[OFMulResult]]
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; LV-NEXT: [[CmpNeg:%[^ ]*]] = icmp ugt i32 [[SubEnd]], 0
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; LV-NEXT: [[CmpPos:%[^ ]*]] = icmp ult i32 [[AddEnd]], 0
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 false, i1 [[CmpNeg]], i1 [[CmpPos]]
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; LV-NEXT: [[BECheck:%[^ ]*]] = icmp ugt i64 [[BE]], 4294967295
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; LV-NEXT: [[CheckOr0:%[^ ]*]] = or i1 [[Cmp]], [[BECheck]]
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; LV-NEXT: [[PredCheck0:%[^ ]*]] = or i1 [[CheckOr0]], [[OFMulOverflow]]
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; LV-NEXT: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV-NEXT: [[OFMul1:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[BE]])
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; LV-NEXT: [[OFMulResult1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 0
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; LV-NEXT: [[OFMulOverflow1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 1
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; LV-NEXT: [[AddEnd1:%[^ ]*]] = add i64 %a2, [[OFMulResult1]]
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; LV-NEXT: [[SubEnd1:%[^ ]*]] = sub i64 %a2, [[OFMulResult1]]
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; LV-NEXT: [[CmpNeg1:%[^ ]*]] = icmp ugt i64 [[SubEnd1]], %a2
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; LV-NEXT: [[CmpPos1:%[^ ]*]] = icmp ult i64 [[AddEnd1]], %a2
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 false, i1 [[CmpNeg1]], i1 [[CmpPos1]]
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; LV-NEXT: [[PredCheck1:%[^ ]*]] = or i1 [[Cmp]], [[OFMulOverflow1]]
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; LV: [[FinalCheck:%[^ ]*]] = or i1 [[Or0]], [[PredCheck1]]
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; LV: br i1 [[FinalCheck]], label %for.body.ph.lver.orig, label %for.body.ph
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define void @f1(i16* noalias %a,
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@ -111,9 +134,31 @@ for.end: ; preds = %for.body
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; LV-LABEL: f2
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; LV-LABEL: for.body.lver.check
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; LV: [[PredCheck0:%[^ ]*]] = icmp ne i128
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; LV: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[PredCheck1:%[^ ]*]] = icmp ne i128
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; LV: [[OFMul:%[^ ]*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[BETrunc:%[^ ]*]])
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; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 0
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; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 1
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; LV-NEXT: [[AddEnd:%[^ ]*]] = add i32 [[Start:%[^ ]*]], [[OFMulResult]]
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; LV-NEXT: [[SubEnd:%[^ ]*]] = sub i32 [[Start]], [[OFMulResult]]
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; LV-NEXT: [[CmpNeg:%[^ ]*]] = icmp ugt i32 [[SubEnd]], [[Start]]
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; LV-NEXT: [[CmpPos:%[^ ]*]] = icmp ult i32 [[AddEnd]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg]], i1 [[CmpPos]]
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; LV-NEXT: [[BECheck:%[^ ]*]] = icmp ugt i64 [[BE]], 4294967295
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; LV-NEXT: [[CheckOr0:%[^ ]*]] = or i1 [[Cmp]], [[BECheck]]
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; LV-NEXT: [[PredCheck0:%[^ ]*]] = or i1 [[CheckOr0]], [[OFMulOverflow]]
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; LV-NEXT: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[OFMul1:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[BE]])
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; LV-NEXT: [[OFMulResult1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 0
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; LV-NEXT: [[OFMulOverflow1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 1
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; LV-NEXT: [[AddEnd1:%[^ ]*]] = add i64 [[Start:%[^ ]*]], [[OFMulResult1]]
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; LV-NEXT: [[SubEnd1:%[^ ]*]] = sub i64 [[Start]], [[OFMulResult1]]
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; LV-NEXT: [[CmpNeg1:%[^ ]*]] = icmp ugt i64 [[SubEnd1]], [[Start]]
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; LV-NEXT: [[CmpPos1:%[^ ]*]] = icmp ult i64 [[AddEnd1]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg1]], i1 [[CmpPos1]]
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; LV-NEXT: [[PredCheck1:%[^ ]*]] = or i1 [[Cmp]], [[OFMulOverflow1]]
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; LV: [[FinalCheck:%[^ ]*]] = or i1 [[Or0]], [[PredCheck1]]
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; LV: br i1 [[FinalCheck]], label %for.body.ph.lver.orig, label %for.body.ph
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define void @f2(i16* noalias %a,
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@ -169,9 +214,31 @@ for.end: ; preds = %for.body
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; LV-LABEL: f3
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; LV-LABEL: for.body.lver.check
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; LV: [[PredCheck0:%[^ ]*]] = icmp ne i128
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; LV: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[PredCheck1:%[^ ]*]] = icmp ne i128
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; LV: [[OFMul:%[^ ]*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[BETrunc:%[^ ]*]])
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; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 0
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; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 1
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; LV-NEXT: [[AddEnd:%[^ ]*]] = add i32 0, [[OFMulResult]]
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; LV-NEXT: [[SubEnd:%[^ ]*]] = sub i32 0, [[OFMulResult]]
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; LV-NEXT: [[CmpNeg:%[^ ]*]] = icmp sgt i32 [[SubEnd]], 0
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; LV-NEXT: [[CmpPos:%[^ ]*]] = icmp slt i32 [[AddEnd]], 0
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 false, i1 [[CmpNeg]], i1 [[CmpPos]]
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; LV-NEXT: [[BECheck:%[^ ]*]] = icmp ugt i64 [[BE]], 4294967295
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; LV-NEXT: [[CheckOr0:%[^ ]*]] = or i1 [[Cmp]], [[BECheck]]
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; LV-NEXT: [[PredCheck0:%[^ ]*]] = or i1 [[CheckOr0]], [[OFMulOverflow]]
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; LV-NEXT: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[OFMul1:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[BE:%[^ ]*]])
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; LV-NEXT: [[OFMulResult1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 0
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; LV-NEXT: [[OFMulOverflow1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 1
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; LV-NEXT: [[AddEnd1:%[^ ]*]] = add i64 %a2, [[OFMulResult1]]
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; LV-NEXT: [[SubEnd1:%[^ ]*]] = sub i64 %a2, [[OFMulResult1]]
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; LV-NEXT: [[CmpNeg1:%[^ ]*]] = icmp ugt i64 [[SubEnd1]], %a2
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; LV-NEXT: [[CmpPos1:%[^ ]*]] = icmp ult i64 [[AddEnd1]], %a2
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 false, i1 [[CmpNeg1]], i1 [[CmpPos1]]
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; LV-NEXT: [[PredCheck1:%[^ ]*]] = or i1 [[Cmp]], [[OFMulOverflow1]]
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; LV: [[FinalCheck:%[^ ]*]] = or i1 [[Or0]], [[PredCheck1]]
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; LV: br i1 [[FinalCheck]], label %for.body.ph.lver.orig, label %for.body.ph
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define void @f3(i16* noalias %a,
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@ -223,9 +290,31 @@ for.end: ; preds = %for.body
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; LV-LABEL: f4
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; LV-LABEL: for.body.lver.check
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; LV: [[PredCheck0:%[^ ]*]] = icmp ne i128
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; LV: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[PredCheck1:%[^ ]*]] = icmp ne i128
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; LV: [[OFMul:%[^ ]*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[BETrunc:%[^ ]*]])
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; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 0
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; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 1
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; LV-NEXT: [[AddEnd:%[^ ]*]] = add i32 [[Start:%[^ ]*]], [[OFMulResult]]
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; LV-NEXT: [[SubEnd:%[^ ]*]] = sub i32 [[Start]], [[OFMulResult]]
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; LV-NEXT: [[CmpNeg:%[^ ]*]] = icmp sgt i32 [[SubEnd]], [[Start]]
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; LV-NEXT: [[CmpPos:%[^ ]*]] = icmp slt i32 [[AddEnd]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg]], i1 [[CmpPos]]
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; LV-NEXT: [[BECheck:%[^ ]*]] = icmp ugt i64 [[BE]], 4294967295
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; LV-NEXT: [[CheckOr0:%[^ ]*]] = or i1 [[Cmp]], [[BECheck]]
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; LV-NEXT: [[PredCheck0:%[^ ]*]] = or i1 [[CheckOr0]], [[OFMulOverflow]]
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; LV-NEXT: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[OFMul1:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[BE:%[^ ]*]])
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; LV-NEXT: [[OFMulResult1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 0
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; LV-NEXT: [[OFMulOverflow1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 1
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; LV-NEXT: [[AddEnd1:%[^ ]*]] = add i64 [[Start:%[^ ]*]], [[OFMulResult1]]
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; LV-NEXT: [[SubEnd1:%[^ ]*]] = sub i64 [[Start]], [[OFMulResult1]]
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; LV-NEXT: [[CmpNeg1:%[^ ]*]] = icmp ugt i64 [[SubEnd1]], [[Start]]
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; LV-NEXT: [[CmpPos1:%[^ ]*]] = icmp ult i64 [[AddEnd1]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg1]], i1 [[CmpPos1]]
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; LV-NEXT: [[PredCheck1:%[^ ]*]] = or i1 [[Cmp]], [[OFMulOverflow1]]
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; LV: [[FinalCheck:%[^ ]*]] = or i1 [[Or0]], [[PredCheck1]]
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; LV: br i1 [[FinalCheck]], label %for.body.ph.lver.orig, label %for.body.ph
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define void @f4(i16* noalias %a,
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@ -280,6 +369,32 @@ for.end: ; preds = %for.body
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; LV-LABEL: f5
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; LV-LABEL: for.body.lver.check
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; LV: [[OFMul:%[^ ]*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[BETrunc:%[^ ]*]])
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; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 0
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; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i32, i1 } [[OFMul]], 1
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; LV-NEXT: [[AddEnd:%[^ ]*]] = add i32 [[Start:%[^ ]*]], [[OFMulResult]]
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; LV-NEXT: [[SubEnd:%[^ ]*]] = sub i32 [[Start]], [[OFMulResult]]
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; LV-NEXT: [[CmpNeg:%[^ ]*]] = icmp sgt i32 [[SubEnd]], [[Start]]
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; LV-NEXT: [[CmpPos:%[^ ]*]] = icmp slt i32 [[AddEnd]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg]], i1 [[CmpPos]]
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; LV-NEXT: [[BECheck:%[^ ]*]] = icmp ugt i64 [[BE]], 4294967295
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; LV-NEXT: [[CheckOr0:%[^ ]*]] = or i1 [[Cmp]], [[BECheck]]
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; LV-NEXT: [[PredCheck0:%[^ ]*]] = or i1 [[CheckOr0]], [[OFMulOverflow]]
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; LV-NEXT: [[Or0:%[^ ]*]] = or i1 false, [[PredCheck0]]
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; LV: [[OFMul1:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[BE:%[^ ]*]])
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; LV-NEXT: [[OFMulResult1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 0
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; LV-NEXT: [[OFMulOverflow1:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul1]], 1
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; LV-NEXT: [[AddEnd1:%[^ ]*]] = add i64 [[Start:%[^ ]*]], [[OFMulResult1]]
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; LV-NEXT: [[SubEnd1:%[^ ]*]] = sub i64 [[Start]], [[OFMulResult1]]
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; LV-NEXT: [[CmpNeg1:%[^ ]*]] = icmp ugt i64 [[SubEnd1]], [[Start]]
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; LV-NEXT: [[CmpPos1:%[^ ]*]] = icmp ult i64 [[AddEnd1]], [[Start]]
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; LV-NEXT: [[Cmp:%[^ ]*]] = select i1 true, i1 [[CmpNeg1]], i1 [[CmpPos1]]
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; LV-NEXT: [[PredCheck1:%[^ ]*]] = or i1 [[Cmp]], [[OFMulOverflow1]]
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; LV: [[FinalCheck:%[^ ]*]] = or i1 [[Or0]], [[PredCheck1]]
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; LV: br i1 [[FinalCheck]], label %for.body.ph.lver.orig, label %for.body.ph
|
||||
define void @f5(i16* noalias %a,
|
||||
i16* noalias %b, i64 %N) {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user