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[ARM][MVE] Combine more extending masked loads
For MVE, don't look at the users of the extending loads so that more as desirable for folding. Differential Revision: https://reviews.llvm.org/D74958
This commit is contained in:
Sam Parker
parent
7247401c11
commit
9d9c7e75ed
@ -15323,6 +15323,9 @@ bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
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return false;
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return false;
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}
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}
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if (Subtarget->hasMVEIntegerOps())
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return true;
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// Don't create a loadext if we can fold the extension into a wide/long
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// Don't create a loadext if we can fold the extension into a wide/long
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// instruction.
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// instruction.
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// If there's more than one user instruction, the loadext is desirable no
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// If there's more than one user instruction, the loadext is desirable no
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229
test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
Normal file
229
test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
Normal file
@ -0,0 +1,229 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -disable-mve-tail-predication=false %s -o - | FileCheck %s
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define dso_local arm_aapcs_vfpcc void @sext_i8(i16* noalias nocapture %a, i8* nocapture readonly %b, i32 %N) {
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; CHECK-LABEL: sext_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: mov r3, r0
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; CHECK-NEXT: dlstp.16 lr, r2
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; CHECK: .LBB0_1: @ %vector.body
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; CHECK: vldrb.s16 q0, [r1], #8
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; CHECK-NEXT: vldrh.u16 q1, [r3], #16
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; CHECK-NEXT: vadd.i16 q0, q1, q0
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; CHECK-NEXT: vstrh.16 q0, [r0]
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: letp lr, .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp8 = icmp eq i32 %N, 0
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br i1 %cmp8, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %N, 7
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%n.vec = and i32 %n.rnd.up, -8
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%trip.count.minus.1 = add i32 %N, -1
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%broadcast.splatinsert10 = insertelement <8 x i32> undef, i32 %trip.count.minus.1, i32 0
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%broadcast.splat11 = shufflevector <8 x i32> %broadcast.splatinsert10, <8 x i32> undef, <8 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <8 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <8 x i32> %broadcast.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
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%induction = or <8 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%0 = getelementptr inbounds i8, i8* %b, i32 %index
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%1 = icmp ule <8 x i32> %induction, %broadcast.splat11
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%2 = bitcast i8* %0 to <8 x i8>*
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%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %2, i32 1, <8 x i1> %1, <8 x i8> undef)
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%3 = sext <8 x i8> %wide.masked.load to <8 x i16>
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%4 = getelementptr inbounds i16, i16* %a, i32 %index
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%5 = bitcast i16* %4 to <8 x i16>*
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%wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %5, i32 2, <8 x i1> %1, <8 x i16> undef)
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%6 = add <8 x i16> %wide.masked.load12, %3
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%7 = bitcast i16* %4 to <8 x i16>*
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call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %6, <8 x i16>* %7, i32 2, <8 x i1> %1)
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%index.next = add i32 %index, 8
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%8 = icmp eq i32 %index.next, %n.vec
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br i1 %8, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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; Function Attrs: nofree norecurse nounwind
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define dso_local arm_aapcs_vfpcc void @zext_i8(i16* noalias nocapture %a, i8* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
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; CHECK-LABEL: zext_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: mov r3, r0
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; CHECK-NEXT: dlstp.16 lr, r2
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; CHECK: .LBB1_1: @ %vector.body
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; CHECK: vldrb.u16 q0, [r1], #8
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; CHECK-NEXT: vldrh.u16 q1, [r3], #16
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; CHECK-NEXT: vadd.i16 q0, q1, q0
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; CHECK-NEXT: vstrh.16 q0, [r0]
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: letp lr, .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp8 = icmp eq i32 %N, 0
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br i1 %cmp8, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %N, 7
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%n.vec = and i32 %n.rnd.up, -8
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%trip.count.minus.1 = add i32 %N, -1
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%broadcast.splatinsert10 = insertelement <8 x i32> undef, i32 %trip.count.minus.1, i32 0
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%broadcast.splat11 = shufflevector <8 x i32> %broadcast.splatinsert10, <8 x i32> undef, <8 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <8 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <8 x i32> %broadcast.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
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%induction = or <8 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%0 = getelementptr inbounds i8, i8* %b, i32 %index
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%1 = icmp ule <8 x i32> %induction, %broadcast.splat11
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%2 = bitcast i8* %0 to <8 x i8>*
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%wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %2, i32 1, <8 x i1> %1, <8 x i8> undef)
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%3 = zext <8 x i8> %wide.masked.load to <8 x i16>
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%4 = getelementptr inbounds i16, i16* %a, i32 %index
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%5 = bitcast i16* %4 to <8 x i16>*
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%wide.masked.load12 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %5, i32 2, <8 x i1> %1, <8 x i16> undef)
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%6 = add <8 x i16> %wide.masked.load12, %3
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%7 = bitcast i16* %4 to <8 x i16>*
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call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %6, <8 x i16>* %7, i32 2, <8 x i1> %1)
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%index.next = add i32 %index, 8
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%8 = icmp eq i32 %index.next, %n.vec
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br i1 %8, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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; Function Attrs: nofree norecurse nounwind
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define dso_local arm_aapcs_vfpcc void @sext_i16(i32* noalias nocapture %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
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; CHECK-LABEL: sext_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: mov r3, r0
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK: .LBB2_1: @ %vector.body
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; CHECK: vldrh.s32 q0, [r1], #8
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; CHECK-NEXT: vldrw.u32 q1, [r3], #16
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; CHECK-NEXT: vadd.i32 q0, q1, q0
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: letp lr, .LBB2_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp6 = icmp eq i32 %N, 0
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br i1 %cmp6, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %N, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %N, -1
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%broadcast.splatinsert8 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0
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%broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%induction = or <4 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3>
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%0 = getelementptr inbounds i16, i16* %b, i32 %index
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%1 = icmp ule <4 x i32> %induction, %broadcast.splat9
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%2 = bitcast i16* %0 to <4 x i16>*
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %2, i32 2, <4 x i1> %1, <4 x i16> undef)
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%3 = sext <4 x i16> %wide.masked.load to <4 x i32>
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%4 = getelementptr inbounds i32, i32* %a, i32 %index
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%5 = bitcast i32* %4 to <4 x i32>*
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%wide.masked.load10 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %5, i32 4, <4 x i1> %1, <4 x i32> undef)
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%6 = add nsw <4 x i32> %wide.masked.load10, %3
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%7 = bitcast i32* %4 to <4 x i32>*
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %6, <4 x i32>* %7, i32 4, <4 x i1> %1)
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%index.next = add i32 %index, 4
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%8 = icmp eq i32 %index.next, %n.vec
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br i1 %8, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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; Function Attrs: nofree norecurse nounwind
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define dso_local arm_aapcs_vfpcc void @zext_i16(i32* noalias nocapture %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
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; CHECK-LABEL: zext_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: mov r3, r0
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK: .LBB3_1: @ %vector.body
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; CHECK: vldrh.u32 q0, [r1], #8
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; CHECK-NEXT: vldrw.u32 q1, [r3], #16
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; CHECK-NEXT: vadd.i32 q0, q1, q0
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: mov r0, r3
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; CHECK-NEXT: letp lr, .LBB3_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp6 = icmp eq i32 %N, 0
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br i1 %cmp6, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %N, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %N, -1
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%broadcast.splatinsert8 = insertelement <4 x i32> undef, i32 %trip.count.minus.1, i32 0
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%broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%induction = or <4 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3>
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%0 = getelementptr inbounds i16, i16* %b, i32 %index
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%1 = icmp ule <4 x i32> %induction, %broadcast.splat9
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%2 = bitcast i16* %0 to <4 x i16>*
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %2, i32 2, <4 x i1> %1, <4 x i16> undef)
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%3 = zext <4 x i16> %wide.masked.load to <4 x i32>
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%4 = getelementptr inbounds i32, i32* %a, i32 %index
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%5 = bitcast i32* %4 to <4 x i32>*
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%wide.masked.load10 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %5, i32 4, <4 x i1> %1, <4 x i32> undef)
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%6 = add <4 x i32> %wide.masked.load10, %3
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%7 = bitcast i32* %4 to <4 x i32>*
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %6, <4 x i32>* %7, i32 4, <4 x i1> %1)
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%index.next = add i32 %index, 4
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%8 = icmp eq i32 %index.next, %n.vec
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br i1 %8, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
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declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
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declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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