mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
[PowerPC] Eliminate integer compare instructions - vol. 3
This patch builds upon https://reviews.llvm.org/rL302810 to add handling for the 64-bit SETEQ patterns. Differential Revision: https://reviews.llvm.org/D33369 llvm-svn: 304286
This commit is contained in:
Nemanja Ivanovic
parent
e7b364c5a9
commit
9dfbc0911d
@ -289,6 +289,10 @@ private:
|
||||
int64_t RHSValue, SDLoc dl);
|
||||
SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
int64_t RHSValue, SDLoc dl);
|
||||
SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
int64_t RHSValue, SDLoc dl);
|
||||
SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
int64_t RHSValue, SDLoc dl);
|
||||
SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts);
|
||||
|
||||
void PeepholePPC64();
|
||||
@ -2849,6 +2853,52 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
|
||||
}
|
||||
}
|
||||
|
||||
/// Produces a zero-extended result of comparing two 64-bit values according to
|
||||
/// the passed condition code.
|
||||
SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
|
||||
ISD::CondCode CC,
|
||||
int64_t RHSValue, SDLoc dl) {
|
||||
bool IsRHSZero = RHSValue == 0;
|
||||
switch (CC) {
|
||||
default: return SDValue();
|
||||
case ISD::SETEQ: {
|
||||
// (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6)
|
||||
// (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6)
|
||||
SDValue Xor = IsRHSZero ? LHS :
|
||||
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
|
||||
SDValue Clz =
|
||||
SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0);
|
||||
return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz,
|
||||
getI64Imm(58, dl), getI64Imm(63, dl)),
|
||||
0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Produces a sign-extended result of comparing two 64-bit values according to
|
||||
/// the passed condition code.
|
||||
SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
|
||||
ISD::CondCode CC,
|
||||
int64_t RHSValue, SDLoc dl) {
|
||||
bool IsRHSZero = RHSValue == 0;
|
||||
switch (CC) {
|
||||
default: return SDValue();
|
||||
case ISD::SETEQ: {
|
||||
// {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1)
|
||||
// (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA)
|
||||
// {addcz.reg, addcz.CA} = (addcarry %a, -1)
|
||||
// (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA)
|
||||
SDValue AddInput = IsRHSZero ? LHS :
|
||||
SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0);
|
||||
SDValue Addic =
|
||||
SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue,
|
||||
AddInput, getI32Imm(~0U, dl)), 0);
|
||||
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic,
|
||||
Addic, Addic.getValue(1)), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Does this SDValue have any uses for which keeping the value in a GPR is
|
||||
/// appropriate. This is meant to be used on values that have type i1 since
|
||||
/// it is somewhat meaningless to ask if values of other types can be kept in
|
||||
@ -2896,30 +2946,35 @@ SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare,
|
||||
ISD::CondCode CC =
|
||||
cast<CondCodeSDNode>(Compare.getOperand(CCOpNum))->get();
|
||||
EVT InputVT = LHS.getValueType();
|
||||
if (InputVT != MVT::i32)
|
||||
if (InputVT != MVT::i32 && InputVT != MVT::i64)
|
||||
return SDValue();
|
||||
|
||||
SDLoc dl(Compare);
|
||||
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
|
||||
int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
|
||||
|
||||
if (ConvOpts == SetccInGPROpts::ZExtInvert ||
|
||||
ConvOpts == SetccInGPROpts::SExtInvert)
|
||||
CC = ISD::getSetCCInverse(CC, true);
|
||||
|
||||
if (ISD::isSignedIntSetCC(CC)) {
|
||||
bool Inputs32Bit = InputVT == MVT::i32;
|
||||
if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) {
|
||||
LHS = signExtendInputIfNeeded(LHS);
|
||||
RHS = signExtendInputIfNeeded(RHS);
|
||||
} else if (ISD::isUnsignedIntSetCC(CC)) {
|
||||
} else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) {
|
||||
LHS = zeroExtendInputIfNeeded(LHS);
|
||||
RHS = zeroExtendInputIfNeeded(RHS);
|
||||
}
|
||||
|
||||
SDLoc dl(Compare);
|
||||
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
|
||||
int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX;
|
||||
bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig ||
|
||||
ConvOpts == SetccInGPROpts::SExtInvert;
|
||||
if (IsSext)
|
||||
|
||||
if (IsSext && Inputs32Bit)
|
||||
return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
|
||||
return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
|
||||
else if (Inputs32Bit)
|
||||
return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
|
||||
else if (IsSext)
|
||||
return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl);
|
||||
return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl);
|
||||
}
|
||||
|
||||
void PPCDAGToDAGISel::transferMemOperands(SDNode *N, SDNode *Result) {
|
||||
|
||||
@ -212,13 +212,14 @@ cleanup:
|
||||
ret i32 %retval.0
|
||||
|
||||
; CHECK-LABEL: @testComplexISEL
|
||||
; CHECK: bc 12, 2, [[TRUE:.LBB[0-9]+]]
|
||||
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
|
||||
; CHECK-NEXT: [[TRUE]]
|
||||
; CHECK-NEXT: addi r3, r12, 0
|
||||
; CHECK-NEXT: [[SUCCESSOR]]
|
||||
; CHECK-NEXT: clrldi r3, r3, 32
|
||||
; CHECK-NEXT: blr
|
||||
; CHECK-DAG: [[LI:r[0-9]+]], 1
|
||||
; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0
|
||||
; CHECK: beq cr0, [[EQ:.LBB[0-9_]+]]
|
||||
; CHECK: blr
|
||||
; CHECK: [[EQ]]
|
||||
; CHECK: xor [[XOR:r[0-9]+]]
|
||||
; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
|
||||
; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
|
||||
}
|
||||
|
||||
!1 = !{!2, !2, i64 0}
|
||||
|
||||
@ -7,8 +7,8 @@
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) {
|
||||
; CHECK-LABEL: test:
|
||||
define signext i32 @logic_ne_32(i32 signext %a, i32 signext %b, i32 signext %c) {
|
||||
; CHECK-LABEL: logic_ne_32:
|
||||
; CHECK: xor r7, r3, r4
|
||||
; CHECK-NEXT: li r6, 55
|
||||
; CHECK-NEXT: xor r5, r5, r6
|
||||
@ -65,5 +65,66 @@ if.end29: ; preds = %if.else
|
||||
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) {
|
||||
; CHECK-LABEL: logic_ne_64:
|
||||
; CHECK: xor r7, r3, r4
|
||||
; CHECK-NEXT: li r6, 55
|
||||
; CHECK-NEXT: xor r5, r5, r6
|
||||
; CHECK-NEXT: or r7, r7, r4
|
||||
; CHECK-NEXT: cntlzd r6, r7
|
||||
; CHECK-NEXT: cntlzd r5, r5
|
||||
; CHECK-NEXT: rldicl r6, r6, 58, 63
|
||||
; CHECK-NEXT: rldicl r5, r5, 58, 63
|
||||
; CHECK-NEXT: or. r5, r6, r5
|
||||
; CHECK-NEXT: bc 4, 1
|
||||
entry:
|
||||
%tobool = icmp eq i64 %a, %b
|
||||
%tobool1 = icmp eq i64 %b, 0
|
||||
%or.cond = and i1 %tobool, %tobool1
|
||||
%tobool3 = icmp eq i64 %c, 55
|
||||
%or.cond5 = or i1 %or.cond, %tobool3
|
||||
br i1 %or.cond5, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%call = tail call i64 @foo64(i64 %a) #2
|
||||
br label %return
|
||||
|
||||
if.end: ; preds = %entry
|
||||
%call4 = tail call i64 @bar64(i64 %b) #2
|
||||
br label %return
|
||||
|
||||
return: ; preds = %if.end, %if.then
|
||||
%retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ]
|
||||
ret i64 %retval.0
|
||||
}
|
||||
|
||||
define void @neg_truncate_i64(i64 *%ptr) {
|
||||
; CHECK-LABEL: neg_truncate_i64:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: ld r3, 0(r3)
|
||||
; CHECK-NEXT: rldicl. r3, r3, 0, 63
|
||||
; CHECK-NEXT: bclr 12, 2, 0
|
||||
; CHECK-NEXT: # BB#1: # %if.end29.thread136
|
||||
; CHECK-NEXT: .LBB3_2: # %if.end29
|
||||
entry:
|
||||
%0 = load i64, i64* %ptr, align 4
|
||||
%rem17127 = and i64 %0, 1
|
||||
%cmp18 = icmp eq i64 %rem17127, 0
|
||||
br label %if.else
|
||||
|
||||
if.else: ; preds = %entry
|
||||
br i1 %cmp18, label %if.end29, label %if.end29.thread136
|
||||
|
||||
if.end29.thread136: ; preds = %if.else
|
||||
unreachable
|
||||
|
||||
if.end29: ; preds = %if.else
|
||||
ret void
|
||||
|
||||
}
|
||||
|
||||
declare signext i32 @foo(i32 signext)
|
||||
declare signext i32 @bar(i32 signext)
|
||||
declare i64 @foo64(i64)
|
||||
declare i64 @bar64(i64)
|
||||
|
||||
134
test/CodeGen/PowerPC/testComparesieqsll.ll
Normal file
134
test/CodeGen/PowerPC/testComparesieqsll.ll
Normal file
@ -0,0 +1,134 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; ModuleID = 'ComparisonTestCases/testComparesieqsll.c'
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_ieqsll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ieqsll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv = zext i1 %cmp to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ieqsll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%sub = sext i1 %cmp to i32
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_ieqsll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_ieqsll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv = zext i1 %cmp to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_ieqsll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_ieqsll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%sub = sext i1 %cmp to i32
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_ieqsll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ieqsll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_ieqsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_ieqsll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_ieqsll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_ieqsll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_ieqsll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_ieqsll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
134
test/CodeGen/PowerPC/testComparesiequll.ll
Normal file
134
test/CodeGen/PowerPC/testComparesiequll.ll
Normal file
@ -0,0 +1,134 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; ModuleID = 'ComparisonTestCases/testComparesiequll.c'
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_iequll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_iequll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv = zext i1 %cmp to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_iequll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%sub = sext i1 %cmp to i32
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_iequll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_iequll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv = zext i1 %cmp to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @test_iequll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_iequll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%sub = sext i1 %cmp to i32
|
||||
ret i32 %sub
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_iequll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_iequll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_iequll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_iequll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_iequll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_iequll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_iequll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_iequll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
133
test/CodeGen/PowerPC/testCompareslleqsll.ll
Normal file
133
test/CodeGen/PowerPC/testCompareslleqsll.ll
Normal file
@ -0,0 +1,133 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lleqsll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lleqsll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lleqsll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lleqsll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_lleqsll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lleqsll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_lleqsll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lleqsll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lleqsll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lleqsll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lleqsll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_lleqsll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lleqsll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_lleqsll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
133
test/CodeGen/PowerPC/testComparesllequll.ll
Normal file
133
test/CodeGen/PowerPC/testComparesllequll.ll
Normal file
@ -0,0 +1,133 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llequll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llequll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llequll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llequll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llequll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llequll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_llequll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llequll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llequll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llequll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llequll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llequll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: xor r3, r3, r4
|
||||
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r12)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llequll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llequll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: cntlzd r3, r3
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: rldicl r3, r3, 58, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_llequll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llequll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addic r3, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: subfe r3, r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp eq i64 %a, 0
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user