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[DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars
It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input. I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used. Differential Revision: https://reviews.llvm.org/D54283 llvm-svn: 346530
This commit is contained in:
Craig Topper
parent
6ebaed2a1d
commit
9e195442a4
@ -16933,12 +16933,15 @@ static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
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SDValue N0 = SVN->getOperand(0);
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SDValue N1 = SVN->getOperand(1);
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if (!N0->hasOneUse() || !N1->hasOneUse())
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if (!N0->hasOneUse())
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return SDValue();
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// If only one of N1,N2 is constant, bail out if it is not ALL_ZEROS as
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// discussed above.
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if (!N1.isUndef()) {
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if (!N1->hasOneUse())
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return SDValue();
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bool N0AnyConst = isAnyConstantBuildVector(N0.getNode());
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bool N1AnyConst = isAnyConstantBuildVector(N1.getNode());
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if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode()))
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@ -17371,7 +17374,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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// Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
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// BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
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if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT))
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if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT))
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if (SDValue Res = combineShuffleOfScalars(SVN, DAG, TLI))
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return Res;
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@ -61,19 +61,15 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x i8> %b) {
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; MIPS32R5EB-NEXT: sw $5, 36($sp)
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; MIPS32R5EB-NEXT: sw $4, 40($sp)
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; MIPS32R5EB-NEXT: lbu $1, 37($sp)
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; MIPS32R5EB-NEXT: sw $1, 20($sp)
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; MIPS32R5EB-NEXT: sw $1, 28($sp)
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; MIPS32R5EB-NEXT: lbu $1, 36($sp)
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; MIPS32R5EB-NEXT: sw $1, 16($sp)
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; MIPS32R5EB-NEXT: sw $1, 20($sp)
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; MIPS32R5EB-NEXT: lbu $1, 41($sp)
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; MIPS32R5EB-NEXT: sw $1, 12($sp)
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; MIPS32R5EB-NEXT: lbu $1, 40($sp)
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; MIPS32R5EB-NEXT: lbu $2, 41($sp)
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; MIPS32R5EB-NEXT: sw $2, 4($sp)
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; MIPS32R5EB-NEXT: sw $1, 0($sp)
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; MIPS32R5EB-NEXT: ld.w $w0, 16($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w0, $w0, $w0
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; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
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; MIPS32R5EB-NEXT: ld.w $w1, 0($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 4($sp)
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; MIPS32R5EB-NEXT: ld.d $w0, 16($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 0($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w1, $w0
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; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
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; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
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@ -166,17 +162,15 @@ define <2 x i8> @i8_2(<2 x i8> %a, <2 x i8> %b) {
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; MIPS32R5EL-NEXT: sw $5, 36($sp)
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; MIPS32R5EL-NEXT: sw $4, 40($sp)
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; MIPS32R5EL-NEXT: lbu $1, 37($sp)
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; MIPS32R5EL-NEXT: sw $1, 20($sp)
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; MIPS32R5EL-NEXT: sw $1, 24($sp)
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; MIPS32R5EL-NEXT: lbu $1, 36($sp)
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; MIPS32R5EL-NEXT: sw $1, 16($sp)
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; MIPS32R5EL-NEXT: lbu $1, 41($sp)
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; MIPS32R5EL-NEXT: sw $1, 4($sp)
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; MIPS32R5EL-NEXT: sw $1, 8($sp)
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; MIPS32R5EL-NEXT: lbu $1, 40($sp)
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; MIPS32R5EL-NEXT: sw $1, 0($sp)
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; MIPS32R5EL-NEXT: ld.w $w0, 16($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w0, $w0, $w0
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; MIPS32R5EL-NEXT: ld.w $w1, 0($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w0, 16($sp)
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; MIPS32R5EL-NEXT: ld.d $w1, 0($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
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; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
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; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
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@ -327,61 +321,47 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x
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; MIPS32R5EB-NEXT: sw $5, 132($sp)
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; MIPS32R5EB-NEXT: sw $4, 136($sp)
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; MIPS32R5EB-NEXT: lbu $1, 133($sp)
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; MIPS32R5EB-NEXT: sw $1, 68($sp)
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; MIPS32R5EB-NEXT: sw $1, 76($sp)
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; MIPS32R5EB-NEXT: lbu $1, 132($sp)
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; MIPS32R5EB-NEXT: sw $1, 64($sp)
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; MIPS32R5EB-NEXT: sw $1, 68($sp)
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; MIPS32R5EB-NEXT: lbu $1, 137($sp)
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; MIPS32R5EB-NEXT: sw $1, 60($sp)
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; MIPS32R5EB-NEXT: lbu $1, 136($sp)
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; MIPS32R5EB-NEXT: lbu $2, 137($sp)
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; MIPS32R5EB-NEXT: sw $2, 52($sp)
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; MIPS32R5EB-NEXT: sw $1, 48($sp)
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; MIPS32R5EB-NEXT: ld.w $w0, 64($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w0, $w0, $w0
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; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
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; MIPS32R5EB-NEXT: ld.w $w1, 48($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 52($sp)
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; MIPS32R5EB-NEXT: ld.d $w0, 64($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 48($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w1, $w0
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; MIPS32R5EB-NEXT: sw $6, 128($sp)
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; MIPS32R5EB-NEXT: lbu $1, 129($sp)
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; MIPS32R5EB-NEXT: sw $1, 84($sp)
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; MIPS32R5EB-NEXT: sw $1, 92($sp)
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; MIPS32R5EB-NEXT: lbu $1, 128($sp)
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; MIPS32R5EB-NEXT: sw $1, 80($sp)
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; MIPS32R5EB-NEXT: ld.w $w1, 80($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 84($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 80($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EB-NEXT: sw $7, 124($sp)
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; MIPS32R5EB-NEXT: lbu $1, 125($sp)
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; MIPS32R5EB-NEXT: sw $1, 100($sp)
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; MIPS32R5EB-NEXT: sw $1, 108($sp)
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; MIPS32R5EB-NEXT: lbu $1, 124($sp)
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; MIPS32R5EB-NEXT: sw $1, 96($sp)
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; MIPS32R5EB-NEXT: ld.w $w1, 96($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 100($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 96($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EB-NEXT: lbu $1, 161($fp)
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; MIPS32R5EB-NEXT: sw $1, 4($sp)
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; MIPS32R5EB-NEXT: sw $1, 12($sp)
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; MIPS32R5EB-NEXT: lbu $1, 160($fp)
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; MIPS32R5EB-NEXT: sw $1, 0($sp)
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; MIPS32R5EB-NEXT: ld.w $w1, 0($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 4($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 0($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EB-NEXT: lbu $1, 165($fp)
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; MIPS32R5EB-NEXT: sw $1, 20($sp)
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; MIPS32R5EB-NEXT: sw $1, 28($sp)
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; MIPS32R5EB-NEXT: lbu $1, 164($fp)
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; MIPS32R5EB-NEXT: sw $1, 16($sp)
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; MIPS32R5EB-NEXT: ld.w $w1, 16($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 20($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 16($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EB-NEXT: lbu $1, 169($fp)
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; MIPS32R5EB-NEXT: sw $1, 36($sp)
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; MIPS32R5EB-NEXT: sw $1, 44($sp)
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; MIPS32R5EB-NEXT: lbu $1, 168($fp)
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; MIPS32R5EB-NEXT: sw $1, 32($sp)
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; MIPS32R5EB-NEXT: ld.w $w1, 32($sp)
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; MIPS32R5EB-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EB-NEXT: shf.w $w1, $w1, 177
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; MIPS32R5EB-NEXT: sw $1, 36($sp)
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; MIPS32R5EB-NEXT: ld.d $w1, 32($sp)
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; MIPS32R5EB-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EB-NEXT: shf.w $w0, $w0, 177
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; MIPS32R5EB-NEXT: copy_s.w $1, $w0[1]
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@ -579,54 +559,47 @@ define <2 x i8> @i8x2_7(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x
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; MIPS32R5EL-NEXT: sw $5, 132($sp)
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; MIPS32R5EL-NEXT: sw $4, 136($sp)
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; MIPS32R5EL-NEXT: lbu $1, 133($sp)
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; MIPS32R5EL-NEXT: sw $1, 68($sp)
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; MIPS32R5EL-NEXT: sw $1, 72($sp)
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; MIPS32R5EL-NEXT: lbu $1, 132($sp)
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; MIPS32R5EL-NEXT: sw $1, 64($sp)
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; MIPS32R5EL-NEXT: lbu $1, 137($sp)
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; MIPS32R5EL-NEXT: sw $1, 52($sp)
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; MIPS32R5EL-NEXT: sw $1, 56($sp)
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; MIPS32R5EL-NEXT: lbu $1, 136($sp)
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; MIPS32R5EL-NEXT: sw $1, 48($sp)
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; MIPS32R5EL-NEXT: ld.w $w0, 64($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w0, $w0, $w0
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; MIPS32R5EL-NEXT: ld.w $w1, 48($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w0, 64($sp)
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; MIPS32R5EL-NEXT: ld.d $w1, 48($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w1, $w0
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; MIPS32R5EL-NEXT: sw $6, 128($sp)
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; MIPS32R5EL-NEXT: lbu $1, 129($sp)
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; MIPS32R5EL-NEXT: sw $1, 84($sp)
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; MIPS32R5EL-NEXT: sw $1, 88($sp)
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; MIPS32R5EL-NEXT: lbu $1, 128($sp)
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; MIPS32R5EL-NEXT: sw $1, 80($sp)
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; MIPS32R5EL-NEXT: ld.w $w1, 80($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w1, 80($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EL-NEXT: sw $7, 124($sp)
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; MIPS32R5EL-NEXT: lbu $1, 125($sp)
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; MIPS32R5EL-NEXT: sw $1, 100($sp)
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; MIPS32R5EL-NEXT: sw $1, 104($sp)
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; MIPS32R5EL-NEXT: lbu $1, 124($sp)
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; MIPS32R5EL-NEXT: sw $1, 96($sp)
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; MIPS32R5EL-NEXT: ld.w $w1, 96($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w1, 96($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EL-NEXT: lbu $1, 161($fp)
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; MIPS32R5EL-NEXT: sw $1, 4($sp)
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; MIPS32R5EL-NEXT: sw $1, 8($sp)
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; MIPS32R5EL-NEXT: lbu $1, 160($fp)
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; MIPS32R5EL-NEXT: sw $1, 0($sp)
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; MIPS32R5EL-NEXT: ld.w $w1, 0($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w1, 0($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EL-NEXT: lbu $1, 165($fp)
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; MIPS32R5EL-NEXT: sw $1, 20($sp)
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; MIPS32R5EL-NEXT: sw $1, 24($sp)
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; MIPS32R5EL-NEXT: lbu $1, 164($fp)
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; MIPS32R5EL-NEXT: sw $1, 16($sp)
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; MIPS32R5EL-NEXT: ld.w $w1, 16($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w1, 16($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EL-NEXT: lbu $1, 169($fp)
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; MIPS32R5EL-NEXT: sw $1, 36($sp)
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; MIPS32R5EL-NEXT: sw $1, 40($sp)
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; MIPS32R5EL-NEXT: lbu $1, 168($fp)
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; MIPS32R5EL-NEXT: sw $1, 32($sp)
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; MIPS32R5EL-NEXT: ld.w $w1, 32($sp)
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; MIPS32R5EL-NEXT: ilvr.w $w1, $w1, $w1
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; MIPS32R5EL-NEXT: ld.d $w1, 32($sp)
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; MIPS32R5EL-NEXT: addv.d $w0, $w0, $w1
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; MIPS32R5EL-NEXT: copy_s.w $1, $w0[0]
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; MIPS32R5EL-NEXT: copy_s.w $2, $w0[2]
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@ -28,10 +28,9 @@ define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext
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; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
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; X32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
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; X32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; X32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
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; X32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
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; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X32-NEXT: retl
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;
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@ -28,10 +28,10 @@ define <8 x i32> @a(<8 x i16> %a) nounwind {
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define <3 x i32> @b(<3 x i16> %a) nounwind {
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; CHECK-LIN-LABEL: b:
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; CHECK-LIN: # %bb.0:
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; CHECK-LIN-NEXT: movd %edi, %xmm0
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; CHECK-LIN-NEXT: pinsrw $1, %esi, %xmm0
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; CHECK-LIN-NEXT: pinsrw $2, %edx, %xmm0
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; CHECK-LIN-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; CHECK-LIN-NEXT: pxor %xmm0, %xmm0
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; CHECK-LIN-NEXT: pinsrw $1, %edi, %xmm0
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; CHECK-LIN-NEXT: pinsrw $3, %esi, %xmm0
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; CHECK-LIN-NEXT: pinsrw $5, %edx, %xmm0
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; CHECK-LIN-NEXT: psrad $16, %xmm0
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; CHECK-LIN-NEXT: retq
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;
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@ -40,10 +40,10 @@ define <3 x i32> @b(<3 x i16> %a) nounwind {
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; CHECK-WIN-NEXT: # kill: def $r8w killed $r8w def $r8d
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; CHECK-WIN-NEXT: # kill: def $dx killed $dx def $edx
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; CHECK-WIN-NEXT: # kill: def $cx killed $cx def $ecx
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; CHECK-WIN-NEXT: movd %ecx, %xmm0
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; CHECK-WIN-NEXT: pinsrw $1, %edx, %xmm0
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; CHECK-WIN-NEXT: pinsrw $2, %r8d, %xmm0
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; CHECK-WIN-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; CHECK-WIN-NEXT: pxor %xmm0, %xmm0
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; CHECK-WIN-NEXT: pinsrw $1, %ecx, %xmm0
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; CHECK-WIN-NEXT: pinsrw $3, %edx, %xmm0
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; CHECK-WIN-NEXT: pinsrw $5, %r8d, %xmm0
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; CHECK-WIN-NEXT: psrad $16, %xmm0
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; CHECK-WIN-NEXT: retq
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%c = sext <3 x i16> %a to <3 x i32>
|
||||
@ -88,11 +88,10 @@ define <8 x i32> @d(<8 x i16> %a) nounwind {
|
||||
define <3 x i32> @e(<3 x i16> %a) nounwind {
|
||||
; CHECK-LIN-LABEL: e:
|
||||
; CHECK-LIN: # %bb.0:
|
||||
; CHECK-LIN-NEXT: movd %edi, %xmm0
|
||||
; CHECK-LIN-NEXT: pinsrw $1, %esi, %xmm0
|
||||
; CHECK-LIN-NEXT: pinsrw $2, %edx, %xmm0
|
||||
; CHECK-LIN-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-LIN-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; CHECK-LIN-NEXT: pxor %xmm0, %xmm0
|
||||
; CHECK-LIN-NEXT: pinsrw $0, %edi, %xmm0
|
||||
; CHECK-LIN-NEXT: pinsrw $2, %esi, %xmm0
|
||||
; CHECK-LIN-NEXT: pinsrw $4, %edx, %xmm0
|
||||
; CHECK-LIN-NEXT: retq
|
||||
;
|
||||
; CHECK-WIN-LABEL: e:
|
||||
@ -100,11 +99,10 @@ define <3 x i32> @e(<3 x i16> %a) nounwind {
|
||||
; CHECK-WIN-NEXT: # kill: def $r8w killed $r8w def $r8d
|
||||
; CHECK-WIN-NEXT: # kill: def $dx killed $dx def $edx
|
||||
; CHECK-WIN-NEXT: # kill: def $cx killed $cx def $ecx
|
||||
; CHECK-WIN-NEXT: movd %ecx, %xmm0
|
||||
; CHECK-WIN-NEXT: pinsrw $1, %edx, %xmm0
|
||||
; CHECK-WIN-NEXT: pinsrw $2, %r8d, %xmm0
|
||||
; CHECK-WIN-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-WIN-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; CHECK-WIN-NEXT: pxor %xmm0, %xmm0
|
||||
; CHECK-WIN-NEXT: pinsrw $0, %ecx, %xmm0
|
||||
; CHECK-WIN-NEXT: pinsrw $2, %edx, %xmm0
|
||||
; CHECK-WIN-NEXT: pinsrw $4, %r8d, %xmm0
|
||||
; CHECK-WIN-NEXT: retq
|
||||
%c = zext <3 x i16> %a to <3 x i32>
|
||||
ret <3 x i32> %c
|
||||
|
||||
@ -1259,29 +1259,29 @@ define <4 x float> @sitofp_2i64_to_4f32_zero(<2 x i64> %a) {
|
||||
;
|
||||
; VEX-LABEL: sitofp_2i64_to_4f32_zero:
|
||||
; VEX: # %bb.0:
|
||||
; VEX-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; VEX-NEXT: vmovq %xmm0, %rax
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; VEX-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero
|
||||
; VEX-NEXT: retq
|
||||
;
|
||||
; AVX512F-LABEL: sitofp_2i64_to_4f32_zero:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vmovq %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
|
||||
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: sitofp_2i64_to_4f32_zero:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovq %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
|
||||
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
|
||||
; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
||||
; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
@ -2058,7 +2058,7 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) {
|
||||
;
|
||||
; VEX-LABEL: uitofp_2i64_to_2f32:
|
||||
; VEX: # %bb.0:
|
||||
; VEX-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; VEX-NEXT: vmovq %xmm0, %rax
|
||||
; VEX-NEXT: testq %rax, %rax
|
||||
; VEX-NEXT: js .LBB40_1
|
||||
; VEX-NEXT: # %bb.2:
|
||||
@ -2072,12 +2072,12 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) {
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1
|
||||
; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1
|
||||
; VEX-NEXT: .LBB40_3:
|
||||
; VEX-NEXT: vmovq %xmm0, %rax
|
||||
; VEX-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; VEX-NEXT: testq %rax, %rax
|
||||
; VEX-NEXT: js .LBB40_4
|
||||
; VEX-NEXT: # %bb.5:
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero
|
||||
; VEX-NEXT: retq
|
||||
; VEX-NEXT: .LBB40_4:
|
||||
; VEX-NEXT: movq %rax, %rcx
|
||||
@ -2086,25 +2086,25 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) {
|
||||
; VEX-NEXT: orq %rcx, %rax
|
||||
; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0
|
||||
; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero
|
||||
; VEX-NEXT: retq
|
||||
;
|
||||
; AVX512F-LABEL: uitofp_2i64_to_2f32:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vmovq %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
|
||||
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: uitofp_2i64_to_2f32:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vmovq %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0
|
||||
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
|
||||
; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
||||
; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
|
||||
@ -47,15 +47,16 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X86-SSE2-NEXT: movd %edx, %xmm0
|
||||
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X86-SSE2-NEXT: movzbl 2(%ecx), %ecx
|
||||
; X86-SSE2-NEXT: movdqa %xmm0, (%esp)
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||||
; X86-SSE2-NEXT: movl (%esp), %edx
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-SSE2-NEXT: shll $8, %esi
|
||||
; X86-SSE2-NEXT: shll $8, %edx
|
||||
; X86-SSE2-NEXT: movzbl (%esp), %esi
|
||||
; X86-SSE2-NEXT: orl %edx, %esi
|
||||
; X86-SSE2-NEXT: movd %esi, %xmm0
|
||||
; X86-SSE2-NEXT: pinsrw $1, %ecx, %xmm0
|
||||
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; X86-SSE2-NEXT: movd %edx, %xmm0
|
||||
; X86-SSE2-NEXT: pinsrw $1, %esi, %xmm0
|
||||
; X86-SSE2-NEXT: movzbl 2(%ecx), %ecx
|
||||
; X86-SSE2-NEXT: shll $8, %ecx
|
||||
; X86-SSE2-NEXT: pinsrw $2, %ecx, %xmm0
|
||||
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X86-SSE2-NEXT: psrad $24, %xmm0
|
||||
; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
|
||||
@ -95,15 +96,16 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X64-SSE2-NEXT: movq %rax, %xmm0
|
||||
; X64-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X64-SSE2-NEXT: movzbl 2(%rsi), %eax
|
||||
; X64-SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; X64-SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax
|
||||
; X64-SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
|
||||
; X64-SSE2-NEXT: shll $8, %ecx
|
||||
; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
|
||||
; X64-SSE2-NEXT: orl %ecx, %edx
|
||||
; X64-SSE2-NEXT: movd %edx, %xmm0
|
||||
; X64-SSE2-NEXT: pinsrw $1, %eax, %xmm0
|
||||
; X64-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; X64-SSE2-NEXT: shll $8, %eax
|
||||
; X64-SSE2-NEXT: movd %eax, %xmm0
|
||||
; X64-SSE2-NEXT: pinsrw $1, %ecx, %xmm0
|
||||
; X64-SSE2-NEXT: movzbl 2(%rsi), %eax
|
||||
; X64-SSE2-NEXT: shll $8, %eax
|
||||
; X64-SSE2-NEXT: pinsrw $2, %eax, %xmm0
|
||||
; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X64-SSE2-NEXT: psrad $24, %xmm0
|
||||
; X64-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
|
||||
|
||||
@ -77,7 +77,6 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X86-SSE2: # %bb.0: # %entry
|
||||
; X86-SSE2-NEXT: pushl %ebp
|
||||
; X86-SSE2-NEXT: movl %esp, %ebp
|
||||
; X86-SSE2-NEXT: pushl %esi
|
||||
; X86-SSE2-NEXT: andl $-16, %esp
|
||||
; X86-SSE2-NEXT: subl $32, %esp
|
||||
; X86-SSE2-NEXT: movl 8(%ebp), %eax
|
||||
@ -88,15 +87,11 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X86-SSE2-NEXT: movzbl 2(%ecx), %ecx
|
||||
; X86-SSE2-NEXT: movdqa %xmm0, (%esp)
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||||
; X86-SSE2-NEXT: shll $8, %edx
|
||||
; X86-SSE2-NEXT: movzbl (%esp), %esi
|
||||
; X86-SSE2-NEXT: orl %edx, %esi
|
||||
; X86-SSE2-NEXT: movd %esi, %xmm0
|
||||
; X86-SSE2-NEXT: pinsrw $1, %ecx, %xmm0
|
||||
; X86-SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
|
||||
; X86-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; X86-SSE2-NEXT: movzbl (%esp), %edx
|
||||
; X86-SSE2-NEXT: movd %edx, %xmm0
|
||||
; X86-SSE2-NEXT: movzbl {{[0-9]+}}(%esp), %edx
|
||||
; X86-SSE2-NEXT: pinsrw $2, %edx, %xmm0
|
||||
; X86-SSE2-NEXT: pinsrw $4, %ecx, %xmm0
|
||||
; X86-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
|
||||
; X86-SSE2-NEXT: movss %xmm0, (%eax)
|
||||
; X86-SSE2-NEXT: movaps %xmm0, %xmm1
|
||||
@ -104,8 +99,7 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X86-SSE2-NEXT: movss %xmm1, 8(%eax)
|
||||
; X86-SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
|
||||
; X86-SSE2-NEXT: movss %xmm0, 4(%eax)
|
||||
; X86-SSE2-NEXT: leal -4(%ebp), %esp
|
||||
; X86-SSE2-NEXT: popl %esi
|
||||
; X86-SSE2-NEXT: movl %ebp, %esp
|
||||
; X86-SSE2-NEXT: popl %ebp
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
@ -135,15 +129,11 @@ define void @convert_v3i8_to_v3f32(<3 x float>* %dst.addr, <3 x i8>* %src.addr)
|
||||
; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
|
||||
; X64-SSE2-NEXT: movzbl 2(%rsi), %eax
|
||||
; X64-SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; X64-SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
|
||||
; X64-SSE2-NEXT: shll $8, %ecx
|
||||
; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
|
||||
; X64-SSE2-NEXT: orl %ecx, %edx
|
||||
; X64-SSE2-NEXT: movd %edx, %xmm0
|
||||
; X64-SSE2-NEXT: pinsrw $1, %eax, %xmm0
|
||||
; X64-SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; X64-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
|
||||
; X64-SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
|
||||
; X64-SSE2-NEXT: movd %ecx, %xmm0
|
||||
; X64-SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
|
||||
; X64-SSE2-NEXT: pinsrw $2, %ecx, %xmm0
|
||||
; X64-SSE2-NEXT: pinsrw $4, %eax, %xmm0
|
||||
; X64-SSE2-NEXT: cvtdq2ps %xmm0, %xmm0
|
||||
; X64-SSE2-NEXT: movlps %xmm0, (%rdi)
|
||||
; X64-SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user