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[DAGCombiner] sink target-supported FP<->int cast op after concat vectors
Try to combine N short vector cast ops into 1 wide vector cast op: concat (cast X), (cast Y)... -> cast (concat X, Y...) This is part of solving PR45794: https://bugs.llvm.org/show_bug.cgi?id=45794 As noted in the code comment, this is uglier than I was hoping because the opcode determines whether we pass the source or destination type to isOperationLegalOrCustom(). Also IIUC, there's no way to validate what the other (dest or src) type is. Without the extra legality check on that, there's an ARM regression test in: test/CodeGen/ARM/isel-v8i32-crash.ll ...that will crash trying to lower an unsupported v8f32 to v8i16. Differential Revision: https://reviews.llvm.org/D79360
This commit is contained in:
Sanjay Patel
parent
674d498a96
commit
9e1d71ddef
@ -18546,6 +18546,69 @@ static SDValue combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) {
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DAG.getBitcast(VT, SV1), Mask, DAG);
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}
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static SDValue combineConcatVectorOfCasts(SDNode *N, SelectionDAG &DAG) {
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unsigned CastOpcode = N->getOperand(0).getOpcode();
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switch (CastOpcode) {
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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// TODO: Allow more opcodes?
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// case ISD::BITCAST:
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// case ISD::TRUNCATE:
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// case ISD::ZERO_EXTEND:
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// case ISD::SIGN_EXTEND:
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// case ISD::FP_EXTEND:
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break;
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default:
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return SDValue();
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}
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EVT SrcVT = N->getOperand(0).getOperand(0).getValueType();
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if (!SrcVT.isVector())
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return SDValue();
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// All operands of the concat must be the same kind of cast from the same
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// source type.
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SmallVector<SDValue, 4> SrcOps;
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for (SDValue Op : N->ops()) {
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if (Op.getOpcode() != CastOpcode || !Op.hasOneUse() ||
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Op.getOperand(0).getValueType() != SrcVT)
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return SDValue();
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SrcOps.push_back(Op.getOperand(0));
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}
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// The wider cast must be supported by the target. This is unusual because
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// the operation support type parameter depends on the opcode. In addition,
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// check the other type in the cast to make sure this is really legal.
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EVT VT = N->getValueType(0);
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EVT SrcEltVT = SrcVT.getVectorElementType();
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unsigned NumElts = SrcVT.getVectorElementCount().Min * N->getNumOperands();
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EVT ConcatSrcVT = EVT::getVectorVT(*DAG.getContext(), SrcEltVT, NumElts);
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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switch (CastOpcode) {
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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if (!TLI.isOperationLegalOrCustom(CastOpcode, ConcatSrcVT) ||
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!TLI.isTypeLegal(VT))
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return SDValue();
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break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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if (!TLI.isOperationLegalOrCustom(CastOpcode, VT) ||
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!TLI.isTypeLegal(ConcatSrcVT))
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return SDValue();
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break;
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default:
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llvm_unreachable("Unexpected cast opcode");
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}
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// concat (cast X), (cast Y)... -> cast (concat X, Y...)
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SDLoc DL(N);
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SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps);
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return DAG.getNode(CastOpcode, DL, VT, NewConcat);
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}
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SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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// If we only have one input vector, we don't need to do any concatenation.
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if (N->getNumOperands() == 1)
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@ -18673,6 +18736,9 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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if (SDValue V = combineConcatVectorOfExtracts(N, DAG))
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return V;
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if (SDValue V = combineConcatVectorOfCasts(N, DAG))
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return V;
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// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
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// nodes often generate nop CONCAT_VECTOR nodes.
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// Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
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@ -167,15 +167,14 @@ define <32 x i8> @vshift12(<32 x i8> %a) {
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define <8 x i32> @vshift08(<8 x i32> %a) {
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; CHECK-LABEL: vshift08:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpslld $23, %xmm0, %xmm1
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vpslld $23, %xmm1, %xmm1
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [1065353216,1065353216,1065353216,1065353216]
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; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vcvttps2dq %xmm1, %xmm1
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
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; CHECK-NEXT: vpslld $23, %xmm0, %xmm0
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; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0
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; CHECK-NEXT: retq
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%bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
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ret <8 x i32> %bitop
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@ -8,16 +8,14 @@
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define <4 x float> @sitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
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; SSE-LABEL: sitofp_v4i32_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: cvtdq2ps %xmm1, %xmm1
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; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sitofp_v4i32_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2ps %xmm1, %xmm1
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; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; AVX-NEXT: retq
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%s0 = sitofp <2 x i32> %x to <2 x float>
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%s1 = sitofp <2 x i32> %y to <2 x float>
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@ -28,68 +26,55 @@ define <4 x float> @sitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
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define <4 x float> @uitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
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; SSE2-LABEL: uitofp_v4i32_v4f32:
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; SSE2: # %bb.0:
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; SSE2-NEXT: xorpd %xmm2, %xmm2
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; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: movapd {{.*#+}} xmm3 = [4.503599627370496E+15,4.503599627370496E+15]
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; SSE2-NEXT: orpd %xmm3, %xmm0
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; SSE2-NEXT: subpd %xmm3, %xmm0
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; SSE2-NEXT: cvtpd2ps %xmm0, %xmm0
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; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
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; SSE2-NEXT: orpd %xmm3, %xmm1
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; SSE2-NEXT: subpd %xmm3, %xmm1
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; SSE2-NEXT: cvtpd2ps %xmm1, %xmm1
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; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: por {{.*}}(%rip), %xmm1
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; SSE2-NEXT: psrld $16, %xmm0
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; SSE2-NEXT: por {{.*}}(%rip), %xmm0
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; SSE2-NEXT: subps {{.*}}(%rip), %xmm0
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; SSE2-NEXT: addps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE4-LABEL: uitofp_v4i32_v4f32:
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; SSE4: # %bb.0:
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; SSE4-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
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; SSE4-NEXT: por %xmm2, %xmm0
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; SSE4-NEXT: subpd %xmm2, %xmm0
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; SSE4-NEXT: cvtpd2ps %xmm0, %xmm0
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; SSE4-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; SSE4-NEXT: por %xmm2, %xmm1
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; SSE4-NEXT: subpd %xmm2, %xmm1
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; SSE4-NEXT: cvtpd2ps %xmm1, %xmm1
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; SSE4-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200]
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; SSE4-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
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; SSE4-NEXT: psrld $16, %xmm0
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; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
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; SSE4-NEXT: subps {{.*}}(%rip), %xmm0
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; SSE4-NEXT: addps %xmm1, %xmm0
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; SSE4-NEXT: retq
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;
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; AVX1-LABEL: uitofp_v4i32_v4f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
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; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vcvtpd2ps %xmm0, %xmm0
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vcvtpd2ps %xmm1, %xmm1
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; AVX1-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
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; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
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; AVX1-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: uitofp_v4i32_v4f32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
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; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vsubpd %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vcvtpd2ps %xmm0, %xmm0
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; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX2-NEXT: vpor %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vsubpd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vcvtpd2ps %xmm1, %xmm1
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; AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
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; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1392508928,1392508928,1392508928,1392508928]
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11]
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; AVX2-NEXT: vsubps %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vaddps %xmm0, %xmm1, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: uitofp_v4i32_v4f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
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; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
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; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0
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; AVX512-NEXT: vcvtudq2ps %zmm1, %zmm1
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; AVX512-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0
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; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%s0 = uitofp <2 x i32> %x to <2 x float>
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@ -101,16 +86,14 @@ define <4 x float> @uitofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
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define <4 x i32> @fptosi_v4f32_v4i32(<2 x float> %x, <2 x float> %y) {
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; SSE-LABEL: fptosi_v4f32_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttps2dq %xmm0, %xmm0
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; SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: cvttps2dq %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fptosi_v4f32_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
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; AVX-NEXT: vcvttps2dq %xmm1, %xmm1
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; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
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; AVX-NEXT: retq
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%s0 = fptosi <2 x float> %x to <2 x i32>
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%s1 = fptosi <2 x float> %y to <2 x i32>
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@ -208,11 +191,9 @@ define <4 x i32> @fptoui_v4f32_v4i32(<2 x float> %x, <2 x float> %y) {
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;
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; AVX512-LABEL: fptoui_v4f32_v4i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
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; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
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; AVX512-NEXT: vcvttps2udq %zmm0, %zmm0
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; AVX512-NEXT: vcvttps2udq %zmm1, %zmm1
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; AVX512-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX512-NEXT: vcvttps2udq %zmm0, %zmm0
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; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%s0 = fptoui <2 x float> %x to <2 x i32>
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@ -230,9 +211,8 @@ define <4 x double> @sitofp_v4i32_v4f64(<2 x i32> %x, <2 x i32> %y) {
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;
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; AVX-LABEL: sitofp_v4i32_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm1, %xmm1
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX-NEXT: retq
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%s0 = sitofp <2 x i32> %x to <2 x double>
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%s1 = sitofp <2 x i32> %y to <2 x double>
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@ -267,34 +247,27 @@ define <4 x double> @uitofp_v4i32_v4f64(<2 x i32> %x, <2 x i32> %y) {
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; AVX1-LABEL: uitofp_v4i32_v4f64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
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; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vsubpd %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
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; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vsubpd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
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; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
|
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; AVX1-NEXT: vorpd %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vsubpd %ymm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: uitofp_v4i32_v4f64:
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; AVX2: # %bb.0:
|
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; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
|
||||
; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vsubpd %xmm2, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
|
||||
; AVX2-NEXT: vpor %xmm2, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vsubpd %xmm2, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
||||
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15,4.503599627370496E+15]
|
||||
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vsubpd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512-LABEL: uitofp_v4i32_v4f64:
|
||||
; AVX512: # %bb.0:
|
||||
; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $ymm1
|
||||
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
||||
; AVX512-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX512-NEXT: vcvtudq2pd %ymm0, %zmm0
|
||||
; AVX512-NEXT: vcvtudq2pd %ymm1, %zmm1
|
||||
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
|
||||
; AVX512-NEXT: retq
|
||||
%s0 = uitofp <2 x i32> %x to <2 x double>
|
||||
%s1 = uitofp <2 x i32> %y to <2 x double>
|
||||
@ -312,9 +285,10 @@ define <4 x i32> @fptosi_v4f64_v4i32(<2 x double> %x, <2 x double> %y) {
|
||||
;
|
||||
; AVX-LABEL: fptosi_v4f64_v4i32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vcvttpd2dq %xmm0, %xmm0
|
||||
; AVX-NEXT: vcvttpd2dq %xmm1, %xmm1
|
||||
; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0
|
||||
; AVX-NEXT: vzeroupper
|
||||
; AVX-NEXT: retq
|
||||
%s0 = fptosi <2 x double> %x to <2 x i32>
|
||||
%s1 = fptosi <2 x double> %y to <2 x i32>
|
||||
@ -404,11 +378,10 @@ define <4 x i32> @fptoui_v4f64_v4i32(<2 x double> %x, <2 x double> %y) {
|
||||
;
|
||||
; AVX512-LABEL: fptoui_v4f64_v4i32:
|
||||
; AVX512: # %bb.0:
|
||||
; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
|
||||
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
|
||||
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
||||
; AVX512-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX512-NEXT: vcvttpd2udq %zmm0, %ymm0
|
||||
; AVX512-NEXT: vcvttpd2udq %zmm1, %ymm1
|
||||
; AVX512-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
|
||||
; AVX512-NEXT: vzeroupper
|
||||
; AVX512-NEXT: retq
|
||||
%s0 = fptoui <2 x double> %x to <2 x i32>
|
||||
@ -417,6 +390,8 @@ define <4 x i32> @fptoui_v4f64_v4i32(<2 x double> %x, <2 x double> %y) {
|
||||
ret <4 x i32> %r
|
||||
}
|
||||
|
||||
; Negative test
|
||||
|
||||
define <4 x float> @mismatch_tofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
|
||||
; SSE2-LABEL: mismatch_tofp_v4i32_v4f32:
|
||||
; SSE2: # %bb.0:
|
||||
@ -477,6 +452,8 @@ define <4 x float> @mismatch_tofp_v4i32_v4f32(<2 x i32> %x, <2 x i32> %y) {
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; Negative test
|
||||
|
||||
define <4 x float> @sitofp_v4i32_v4f32_extra_use(<2 x i32> %x, <2 x i32> %y, <2 x float>* %p) {
|
||||
; SSE-LABEL: sitofp_v4i32_v4f32_extra_use:
|
||||
; SSE: # %bb.0:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user