RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

[DAG] Improve store merge candidate pruning.

Browse Source 
Remove non-consecutive stores from store merge candidate search as
they cannot be merged and will prevent us from finding subsequent
mergeable store cases.

Reviewers: jyknight, bogner, javed.absar, spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32086

llvm-svn: 300561
This commit is contained in:
Nirav Dave 2017-04-18 15:36:34 +00:00
parent 23e3be6e6e
commit 9e2d41cff4
3 changed files with 25 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -12375,6 +12375,27 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
return LHS.OffsetFromBase < RHS.OffsetFromBase;
});
// Store Merge attempts to merge the lowest stores. This generally
// works out as if successful, as the remaining stores are checked
// after the first collection of stores is merged. However, in the
// case that a non-mergeable store is found first, e.g., {p[-2],
// p[0], p[1], p[2], p[3]}, we would fail and miss the subsequent
// mergeable cases. To prevent this, we prune such stores from the
// front of StoreNodes here.
unsigned StartIdx = 0;
while ((StartIdx + 1 < StoreNodes.size()) &&
StoreNodes[StartIdx].OffsetFromBase + ElementSizeBytes !=
StoreNodes[StartIdx + 1].OffsetFromBase)
++StartIdx;
// Bail if we don't have enough candidates to merge.
if (StartIdx + 1 >= StoreNodes.size())
return false;
if (StartIdx)
StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + StartIdx);
// Scan the memory operations on the chain and find the first non-consecutive
// store memory address.
unsigned NumConsecutiveStores = 0;

4
test/CodeGen/AArch64/arm64-abi.ll
View File

@ -43,9 +43,7 @@ entry:
; CHECK-LABEL: i8i16caller
; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
; They are i8, i16, i8 and i8.
; CHECK-DAG: strb {{w[0-9]+}}, [sp, #5]
; CHECK-DAG: strb {{w[0-9]+}}, [sp, #4]
; CHECK-DAG: strh {{w[0-9]+}}, [sp, #2]
; CHECK-DAG: stur {{w[0-9]+}}, [sp, #2]
; CHECK-DAG: strb {{w[0-9]+}}, [sp]
; CHECK: bl
; FAST-LABEL: i8i16caller

12
test/CodeGen/X86/MergeConsecutiveStores.ll
View File

@ -596,14 +596,8 @@ define void @almost_consecutive_stores(i8* %p) {
store i8 3, i8* %p3
ret void
; CHECK-LABEL: almost_consecutive_stores
; CHECK-DAG: movb $0, (%rdi)
; CHECK-DAG: movb $1, 42(%rdi)
; CHECK-DAG: movb $2, 2(%rdi)
; CHECK-DAG: movb $3, 3(%rdi)
; CHECK-DAG: movb $0, (%rdi)
; CHECK-DAG: movb $1, 42(%rdi)
; CHECK-DAG: movw $770, 2(%rdi)
; CHECK: retq
; We should able to merge the final two stores into a 16-bit store
; FIXMECHECK-DAG: movw $770, 2(%rdi)
}