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[PowerPC] Implement lowering for atomicrmw min/max/umin/umax
Implement lowering for atomicrmw min/max/umin/umax. Fixes PR28818. llvm-svn: 279933
This commit is contained in:
Hal Finkel
parent
eed0bb3d71
commit
9e501da293
@ -8387,7 +8387,9 @@ Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
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MachineBasicBlock *
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PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
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unsigned AtomicSize,
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unsigned BinOpcode) const {
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unsigned BinOpcode,
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unsigned CmpOpcode,
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unsigned CmpPred) const {
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// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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@ -8427,8 +8429,12 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
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DebugLoc dl = MI.getDebugLoc();
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MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB =
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CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
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MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loopMBB);
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if (CmpOpcode)
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F->insert(It, loop2MBB);
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F->insert(It, exitMBB);
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exitMBB->splice(exitMBB->begin(), BB,
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std::next(MachineBasicBlock::iterator(MI)), BB->end());
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@ -8450,11 +8456,31 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
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// st[wd]cx. r0, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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// For max/min...
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// loopMBB:
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// l[wd]arx dest, ptr
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// cmpl?[wd] incr, dest
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// bgt exitMBB
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// loop2MBB:
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// st[wd]cx. dest, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
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.addReg(ptrA).addReg(ptrB);
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if (BinOpcode)
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BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
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if (CmpOpcode) {
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BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
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.addReg(incr).addReg(dest);
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BuildMI(BB, dl, TII->get(PPC::BCC))
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.addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
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BB->addSuccessor(loop2MBB);
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BB->addSuccessor(exitMBB);
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BB = loop2MBB;
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}
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BuildMI(BB, dl, TII->get(StoreMnemonic))
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.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
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BuildMI(BB, dl, TII->get(PPC::BCC))
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@ -8472,10 +8498,13 @@ MachineBasicBlock *
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PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
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MachineBasicBlock *BB,
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bool is8bit, // operation
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unsigned BinOpcode) const {
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unsigned BinOpcode,
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unsigned CmpOpcode,
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unsigned CmpPred) const {
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// If we support part-word atomic mnemonics, just use them
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if (Subtarget.hasPartwordAtomics())
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return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
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return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode,
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CmpOpcode, CmpPred);
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// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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@ -8497,8 +8526,12 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
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DebugLoc dl = MI.getDebugLoc();
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MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *loop2MBB =
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CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr;
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MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loopMBB);
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if (CmpOpcode)
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F->insert(It, loop2MBB);
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F->insert(It, exitMBB);
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exitMBB->splice(exitMBB->begin(), BB,
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std::next(MachineBasicBlock::iterator(MI)), BB->end());
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@ -8583,6 +8616,32 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr &MI,
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.addReg(TmpDestReg).addReg(MaskReg);
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BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
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.addReg(TmpReg).addReg(MaskReg);
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if (CmpOpcode) {
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// For unsigned comparisons, we can directly compare the shifted values.
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// For signed comparisons we shift and sign extend.
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unsigned SReg = RegInfo.createVirtualRegister(RC);
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BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), SReg)
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.addReg(TmpDestReg).addReg(MaskReg);
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unsigned ValueReg = SReg;
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unsigned CmpReg = Incr2Reg;
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if (CmpOpcode == PPC::CMPW) {
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ValueReg = RegInfo.createVirtualRegister(RC);
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BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
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.addReg(SReg).addReg(ShiftReg);
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unsigned ValueSReg = RegInfo.createVirtualRegister(RC);
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BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
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.addReg(ValueReg);
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ValueReg = ValueSReg;
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CmpReg = incr;
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}
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BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
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.addReg(CmpReg).addReg(ValueReg);
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BuildMI(BB, dl, TII->get(PPC::BCC))
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.addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
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BB->addSuccessor(loop2MBB);
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BB->addSuccessor(exitMBB);
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BB = loop2MBB;
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}
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BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
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.addReg(Tmp3Reg).addReg(Tmp2Reg);
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BuildMI(BB, dl, TII->get(PPC::STWCX))
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@ -9089,6 +9148,42 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
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BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
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BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
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BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
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BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
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BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
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BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
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BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
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BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
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BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
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BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
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BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
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BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
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BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE);
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else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
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else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
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@ -589,11 +589,15 @@ namespace llvm {
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MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
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MachineBasicBlock *MBB,
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unsigned AtomicSize,
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unsigned BinOpcode) const;
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unsigned BinOpcode,
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unsigned CmpOpcode = 0,
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unsigned CmpPred = 0) const;
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MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
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MachineBasicBlock *MBB,
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bool is8bit,
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unsigned Opcode) const;
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unsigned Opcode,
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unsigned CmpOpcode = 0,
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unsigned CmpPred = 0) const;
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MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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@ -224,6 +224,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
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[(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_MIN_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MIN_I64",
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[(set i64:$dst, (atomic_load_min_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_MAX_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_MAX_I64",
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[(set i64:$dst, (atomic_load_max_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_UMIN_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMIN_I64",
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[(set i64:$dst, (atomic_load_umin_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_UMAX_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_UMAX_I64",
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[(set i64:$dst, (atomic_load_umax_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_CMP_SWAP_I64 : Pseudo<
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
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@ -1509,6 +1509,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
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[(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MIN_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8",
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[(set i32:$dst, (atomic_load_min_8 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MAX_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8",
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[(set i32:$dst, (atomic_load_max_8 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMIN_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8",
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[(set i32:$dst, (atomic_load_umin_8 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMAX_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8",
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[(set i32:$dst, (atomic_load_umax_8 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_ADD_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
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[(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
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@ -1527,6 +1539,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
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[(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MIN_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16",
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[(set i32:$dst, (atomic_load_min_16 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MAX_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16",
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[(set i32:$dst, (atomic_load_max_16 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMIN_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16",
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[(set i32:$dst, (atomic_load_umin_16 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMAX_I16 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16",
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[(set i32:$dst, (atomic_load_umax_16 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_ADD_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
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[(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
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@ -1545,6 +1569,18 @@ let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_NAND_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
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[(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MIN_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32",
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[(set i32:$dst, (atomic_load_min_32 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_MAX_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32",
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[(set i32:$dst, (atomic_load_max_32 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMIN_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32",
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[(set i32:$dst, (atomic_load_umin_32 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_LOAD_UMAX_I32 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32",
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[(set i32:$dst, (atomic_load_umax_32 xoaddr:$ptr, i32:$incr))]>;
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def ATOMIC_CMP_SWAP_I8 : Pseudo<
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(outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
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435
test/CodeGen/PowerPC/atomic-minmax.ll
Normal file
435
test/CodeGen/PowerPC/atomic-minmax.ll
Normal file
@ -0,0 +1,435 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @a32min(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
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entry:
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%0 = atomicrmw min i32* %minimum, i32 %val monotonic
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ret void
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; CHECK-LABEL: @a32min
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; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
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; CHECK: cmpw 4, [[OLDV]]
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; CHECK: bgelr 0
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; CHECK: stwcx. 4, 0, 3
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; CHECK: bne 0,
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; CHECK: blr
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}
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define void @a32max(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
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entry:
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%0 = atomicrmw max i32* %minimum, i32 %val monotonic
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ret void
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; CHECK-LABEL: @a32max
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; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
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; CHECK: cmpw 4, [[OLDV]]
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; CHECK: blelr 0
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; CHECK: stwcx. 4, 0, 3
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; CHECK: bne 0,
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; CHECK: blr
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}
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define void @a32umin(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
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entry:
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%0 = atomicrmw umin i32* %minimum, i32 %val monotonic
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ret void
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; CHECK-LABEL: @a32umin
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; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
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; CHECK: cmplw 4, [[OLDV]]
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; CHECK: bgelr 0
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; CHECK: stwcx. 4, 0, 3
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; CHECK: bne 0,
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; CHECK: blr
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}
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define void @a32umax(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
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entry:
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%0 = atomicrmw umax i32* %minimum, i32 %val monotonic
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ret void
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; CHECK-LABEL: @a32umax
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; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
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; CHECK: cmplw 4, [[OLDV]]
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; CHECK: blelr 0
|
||||
; CHECK: stwcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw min i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a16min
|
||||
; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpw 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: sthcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw max i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a16max
|
||||
; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpw 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: sthcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw umin i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a16umin
|
||||
; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmplw 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: sthcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw umax i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a16umax
|
||||
; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmplw 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: sthcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw min i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a8min
|
||||
; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpw 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: stbcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw max i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a8max
|
||||
; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpw 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: stbcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw umin i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a8umin
|
||||
; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmplw 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: stbcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
|
||||
entry:
|
||||
%0 = atomicrmw umax i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a8umax
|
||||
; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmplw 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: stbcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a64min(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw min i64* %minimum, i64 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a64min
|
||||
; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpd 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: stdcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a64max(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw max i64* %minimum, i64 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a64max
|
||||
; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpd 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: stdcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a64umin(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umin i64* %minimum, i64 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a64umin
|
||||
; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpld 4, [[OLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: stdcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @a64umax(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umax i64* %minimum, i64 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @a64umax
|
||||
; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: cmpld 4, [[OLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: stdcx. 4, 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw min i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae16min
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 0
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
|
||||
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
|
||||
; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
|
||||
; CHECK: cmpw 0, 4, [[SESMOLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw max i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae16max
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 0
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
|
||||
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
|
||||
; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
|
||||
; CHECK: cmpw 0, 4, [[SESMOLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umin i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae16umin
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 0
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
|
||||
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: cmplw 0, 4, [[MOLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umax i16* %minimum, i16 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae16umax
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 0
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
|
||||
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: cmplw 0, 4, [[MOLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw min i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae8min
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 255
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
|
||||
; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
|
||||
; CHECK: cmpw 0, 4, [[SESMOLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw max i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae8max
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 255
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
|
||||
; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
|
||||
; CHECK: cmpw 0, 4, [[SESMOLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umin i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae8umin
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 255
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: cmplw 0, 4, [[MOLDV]]
|
||||
; CHECK: bgelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
define void @ae8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
|
||||
entry:
|
||||
%0 = atomicrmw umax i8* %minimum, i8 %val monotonic
|
||||
ret void
|
||||
|
||||
; CHECK-LABEL: @ae8umax
|
||||
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
|
||||
; CHECK-DAG: li [[M1:[0-9]+]], 255
|
||||
; CHECK-DAG: rldicr 3, 3, 0, 61
|
||||
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
|
||||
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
|
||||
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
|
||||
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
|
||||
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
|
||||
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: cmplw 0, 4, [[MOLDV]]
|
||||
; CHECK: blelr 0
|
||||
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
|
||||
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
|
||||
; CHECK: stwcx. [[NEWV]], 0, 3
|
||||
; CHECK: bne 0,
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="ppc64" }
|
||||
attributes #1 = { nounwind "target-cpu"="pwr8" }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user