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[AArch64] Promote f16 operations to f32.
For the most common ones (such as fadd), we already did the promotion. Do the same thing for all the others. Currently, we'll just crash/assert on all these operations, as there's no hardware or libcall support whatsoever. f16 (half) is specified as an interchange - not arithmetic - format, and is expected to be promoted to single-precision for arithmetic operations. While there, teach the legalizer about promoting some of the (mostly floating-point) operations that we never needed before. Differential Revision: http://reviews.llvm.org/D8648 See related discussion on the thread for: http://reviews.llvm.org/D8755 llvm-svn: 234550
This commit is contained in:
Ahmed Bougacha
parent
5c0e16778c
commit
9e6b267c41
@ -4033,6 +4033,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Node->getOpcode() == ISD::SETCC) {
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OVT = Node->getOperand(0).getSimpleValueType();
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}
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if (Node->getOpcode() == ISD::BR_CC)
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OVT = Node->getOperand(2).getSimpleValueType();
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MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
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SDLoc dl(Node);
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SDValue Tmp1, Tmp2, Tmp3;
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@ -4188,11 +4190,28 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Tmp1, Tmp2, Node->getOperand(2)));
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break;
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}
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case ISD::BR_CC: {
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unsigned ExtOp = ISD::FP_EXTEND;
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if (NVT.isInteger()) {
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ISD::CondCode CCCode =
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cast<CondCodeSDNode>(Node->getOperand(1))->get();
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ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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}
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Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
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Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
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Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
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Node->getOperand(0), Node->getOperand(1),
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Tmp1, Tmp2, Node->getOperand(4)));
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break;
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}
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case ISD::FCOPYSIGN:
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case ISD::FPOW: {
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Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
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@ -4201,10 +4220,40 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Tmp3, DAG.getIntPtrConstant(0)));
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break;
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}
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case ISD::FLOG2:
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case ISD::FEXP2:
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case ISD::FMA: {
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Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
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Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
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Results.push_back(
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DAG.getNode(ISD::FP_ROUND, dl, OVT,
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DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
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DAG.getIntPtrConstant(0)));
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break;
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}
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case ISD::FPOWI: {
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Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
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Tmp2 = Node->getOperand(1);
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Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
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Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
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Tmp3, DAG.getIntPtrConstant(0)));
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break;
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}
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FROUND:
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case ISD::FTRUNC:
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case ISD::FNEG:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FLOG:
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case ISD::FEXP: {
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case ISD::FLOG2:
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case ISD::FLOG10:
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case ISD::FABS:
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case ISD::FEXP:
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case ISD::FEXP2: {
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Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
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Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
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@ -281,14 +281,39 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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// f16 is storage-only, so we promote operations to f32 if we know this is
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// valid, and ignore them otherwise. The operations not mentioned here will
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// fail to select, but this is not a major problem as no source language
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// should be emitting native f16 operations yet.
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setOperationAction(ISD::FADD, MVT::f16, Promote);
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setOperationAction(ISD::FDIV, MVT::f16, Promote);
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setOperationAction(ISD::FMUL, MVT::f16, Promote);
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setOperationAction(ISD::FSUB, MVT::f16, Promote);
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// f16 is a storage-only type, always promote it to f32.
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setOperationAction(ISD::SETCC, MVT::f16, Promote);
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setOperationAction(ISD::BR_CC, MVT::f16, Promote);
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setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
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setOperationAction(ISD::SELECT, MVT::f16, Promote);
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setOperationAction(ISD::FADD, MVT::f16, Promote);
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setOperationAction(ISD::FSUB, MVT::f16, Promote);
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setOperationAction(ISD::FMUL, MVT::f16, Promote);
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setOperationAction(ISD::FDIV, MVT::f16, Promote);
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setOperationAction(ISD::FREM, MVT::f16, Promote);
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setOperationAction(ISD::FMA, MVT::f16, Promote);
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setOperationAction(ISD::FNEG, MVT::f16, Promote);
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setOperationAction(ISD::FABS, MVT::f16, Promote);
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setOperationAction(ISD::FCEIL, MVT::f16, Promote);
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setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
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setOperationAction(ISD::FCOS, MVT::f16, Promote);
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setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
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setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
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setOperationAction(ISD::FPOW, MVT::f16, Promote);
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setOperationAction(ISD::FPOWI, MVT::f16, Promote);
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setOperationAction(ISD::FRINT, MVT::f16, Promote);
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setOperationAction(ISD::FSIN, MVT::f16, Promote);
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setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
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setOperationAction(ISD::FSQRT, MVT::f16, Promote);
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setOperationAction(ISD::FEXP, MVT::f16, Promote);
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setOperationAction(ISD::FEXP2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG, MVT::f16, Promote);
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setOperationAction(ISD::FLOG2, MVT::f16, Promote);
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setOperationAction(ISD::FLOG10, MVT::f16, Promote);
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setOperationAction(ISD::FROUND, MVT::f16, Promote);
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setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
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setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
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setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
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// v4f16 is also a storage-only type, so promote it to v4f32 when that is
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// known to be safe.
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@ -1558,6 +1583,14 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
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if (Op.getOperand(0).getValueType().isVector())
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return LowerVectorFP_TO_INT(Op, DAG);
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// f16 conversions are promoted to f32.
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if (Op.getOperand(0).getValueType() == MVT::f16) {
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SDLoc dl(Op);
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return DAG.getNode(
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Op.getOpcode(), dl, Op.getValueType(),
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DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
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}
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if (Op.getOperand(0).getValueType() != MVT::f128) {
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// It's legal except when f128 is involved
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return Op;
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@ -1607,6 +1640,15 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
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if (Op.getValueType().isVector())
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return LowerVectorINT_TO_FP(Op, DAG);
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// f16 conversions are promoted to f32.
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if (Op.getValueType() == MVT::f16) {
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SDLoc dl(Op);
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return DAG.getNode(
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ISD::FP_ROUND, dl, MVT::f16,
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DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
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DAG.getIntPtrConstant(0));
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}
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// i128 conversions are libcalls.
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if (Op.getOperand(0).getValueType() == MVT::i128)
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return SDValue();
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765
test/CodeGen/AArch64/f16-instructions.ll
Normal file
765
test/CodeGen/AArch64/f16-instructions.ll
Normal file
@ -0,0 +1,765 @@
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: test_fadd:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_fadd(half %a, half %b) #0 {
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%r = fadd half %a, %b
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ret half %r
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}
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; CHECK-LABEL: test_fsub:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fsub s0, s0, s1
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_fsub(half %a, half %b) #0 {
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%r = fsub half %a, %b
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ret half %r
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}
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; CHECK-LABEL: test_fmul:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fmul s0, s0, s1
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_fmul(half %a, half %b) #0 {
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%r = fmul half %a, %b
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ret half %r
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}
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; CHECK-LABEL: test_fdiv:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fdiv s0, s0, s1
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_fdiv(half %a, half %b) #0 {
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%r = fdiv half %a, %b
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ret half %r
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}
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; CHECK-LABEL: test_frem:
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; CHECK-NEXT: stp x29, x30, [sp, #-16]!
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: bl {{_?}}fmodf
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ldp x29, x30, [sp], #16
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; CHECK-NEXT: ret
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define half @test_frem(half %a, half %b) #0 {
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%r = frem half %a, %b
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ret half %r
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}
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; CHECK-LABEL: test_store:
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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define void @test_store(half %a, half* %b) #0 {
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store half %a, half* %b
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ret void
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}
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; CHECK-LABEL: test_load:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: ret
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define half @test_load(half* %a) #0 {
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%r = load half, half* %a
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ret half %r
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}
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declare half @test_callee(half %a, half %b) #0
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; CHECK-LABEL: test_call:
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; CHECK-NEXT: stp x29, x30, [sp, #-16]!
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: bl {{_?}}test_callee
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; CHECK-NEXT: ldp x29, x30, [sp], #16
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; CHECK-NEXT: ret
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define half @test_call(half %a, half %b) #0 {
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%r = call half @test_callee(half %a, half %b)
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ret half %r
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}
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; CHECK-LABEL: test_call_flipped:
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; CHECK-NEXT: stp x29, x30, [sp, #-16]!
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: mov.16b v2, v0
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; CHECK-NEXT: mov.16b v0, v1
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; CHECK-NEXT: mov.16b v1, v2
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; CHECK-NEXT: bl {{_?}}test_callee
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; CHECK-NEXT: ldp x29, x30, [sp], #16
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; CHECK-NEXT: ret
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define half @test_call_flipped(half %a, half %b) #0 {
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%r = call half @test_callee(half %b, half %a)
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ret half %r
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}
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; CHECK-LABEL: test_tailcall_flipped:
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; CHECK-NEXT: mov.16b v2, v0
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; CHECK-NEXT: mov.16b v0, v1
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; CHECK-NEXT: mov.16b v1, v2
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; CHECK-NEXT: b {{_?}}test_callee
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define half @test_tailcall_flipped(half %a, half %b) #0 {
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%r = tail call half @test_callee(half %b, half %a)
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ret half %r
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}
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; CHECK-LABEL: test_select:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: fcsel s0, s0, s1, ne
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
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%r = select i1 %c, half %a, half %b
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ret half %r
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}
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; CHECK-LABEL: test_select_cc:
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; CHECK-DAG: fcvt s3, h3
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; CHECK-DAG: fcvt s2, h2
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; CHECK-DAG: fcvt s1, h1
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; CHECK-DAG: fcvt s0, h0
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; CHECK-DAG: fcmp s2, s3
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; CHECK-DAG: cset [[CC:w[0-9]+]], ne
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; CHECK-DAG: cmp [[CC]], #0
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; CHECK-NEXT: fcsel s0, s0, s1, ne
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {
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%cc = fcmp une half %c, %d
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%r = select i1 %cc, half %a, half %b
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ret half %r
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}
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; CHECK-LABEL: test_fcmp_une:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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define i1 @test_fcmp_une(half %a, half %b) #0 {
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%r = fcmp une half %a, %b
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ret i1 %r
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}
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; CHECK-LABEL: test_fcmp_ueq:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
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; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, eq
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; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], vs
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; CHECK-NEXT: ret
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define i1 @test_fcmp_ueq(half %a, half %b) #0 {
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%r = fcmp ueq half %a, %b
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ret i1 %r
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}
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; CHECK-LABEL: test_fcmp_ugt:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, hi
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; CHECK-NEXT: ret
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define i1 @test_fcmp_ugt(half %a, half %b) #0 {
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%r = fcmp ugt half %a, %b
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ret i1 %r
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}
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; CHECK-LABEL: test_fcmp_uge:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, pl
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; CHECK-NEXT: ret
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define i1 @test_fcmp_uge(half %a, half %b) #0 {
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%r = fcmp uge half %a, %b
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ret i1 %r
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}
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; CHECK-LABEL: test_fcmp_ult:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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define i1 @test_fcmp_ult(half %a, half %b) #0 {
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%r = fcmp ult half %a, %b
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ret i1 %r
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}
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; CHECK-LABEL: test_fcmp_ule:
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w0, le
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; CHECK-NEXT: ret
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define i1 @test_fcmp_ule(half %a, half %b) #0 {
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||||
%r = fcmp ule half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: test_fcmp_uno:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, vs
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_uno(half %a, half %b) #0 {
|
||||
%r = fcmp uno half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_one:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1
|
||||
; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, mi
|
||||
; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], gt
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_one(half %a, half %b) #0 {
|
||||
%r = fcmp one half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_oeq:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, eq
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_oeq(half %a, half %b) #0 {
|
||||
%r = fcmp oeq half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_ogt:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, gt
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_ogt(half %a, half %b) #0 {
|
||||
%r = fcmp ogt half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_oge:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, ge
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_oge(half %a, half %b) #0 {
|
||||
%r = fcmp oge half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_olt:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, mi
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_olt(half %a, half %b) #0 {
|
||||
%r = fcmp olt half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_ole:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, ls
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_ole(half %a, half %b) #0 {
|
||||
%r = fcmp ole half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fcmp_ord:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: cset w0, vc
|
||||
; CHECK-NEXT: ret
|
||||
define i1 @test_fcmp_ord(half %a, half %b) #0 {
|
||||
%r = fcmp ord half %a, %b
|
||||
ret i1 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_br_cc:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcmp s0, s1
|
||||
; CHECK-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]]
|
||||
; CHECK-NEXT: str wzr, [x0]
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: [[BRCC_ELSE]]:
|
||||
; CHECK-NEXT: str wzr, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 {
|
||||
%c = fcmp uge half %a, %b
|
||||
br i1 %c, label %then, label %else
|
||||
then:
|
||||
store i32 0, i32* %p1
|
||||
ret void
|
||||
else:
|
||||
store i32 0, i32* %p2
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_phi:
|
||||
; CHECK: mov x[[PTR:[0-9]+]], x0
|
||||
; CHECK: ldr h[[AB:[0-9]+]], [x[[PTR]]]
|
||||
; CHECK: [[LOOP:LBB[0-9_]+]]:
|
||||
; CHECK: mov.16b v[[R:[0-9]+]], v[[AB]]
|
||||
; CHECK: ldr h[[AB]], [x[[PTR]]]
|
||||
; CHECK: mov x0, x[[PTR]]
|
||||
; CHECK: bl {{_?}}test_dummy
|
||||
; CHECK: mov.16b v0, v[[R]]
|
||||
; CHECK: ret
|
||||
define half @test_phi(half* %p1) #0 {
|
||||
entry:
|
||||
%a = load half, half* %p1
|
||||
br label %loop
|
||||
loop:
|
||||
%r = phi half [%a, %entry], [%b, %loop]
|
||||
%b = load half, half* %p1
|
||||
%c = call i1 @test_dummy(half* %p1)
|
||||
br i1 %c, label %loop, label %return
|
||||
return:
|
||||
ret half %r
|
||||
}
|
||||
declare i1 @test_dummy(half* %p1) #0
|
||||
|
||||
; CHECK-LABEL: test_fptosi_i32:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvtzs w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define i32 @test_fptosi_i32(half %a) #0 {
|
||||
%r = fptosi half %a to i32
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fptosi_i64:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvtzs x0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define i64 @test_fptosi_i64(half %a) #0 {
|
||||
%r = fptosi half %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fptoui_i32:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvtzu w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define i32 @test_fptoui_i32(half %a) #0 {
|
||||
%r = fptoui half %a to i32
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fptoui_i64:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvtzu x0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define i64 @test_fptoui_i64(half %a) #0 {
|
||||
%r = fptoui half %a to i64
|
||||
ret i64 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_uitofp_i32:
|
||||
; CHECK-NEXT: ucvtf s0, w0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_uitofp_i32(i32 %a) #0 {
|
||||
%r = uitofp i32 %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_uitofp_i64:
|
||||
; CHECK-NEXT: ucvtf s0, x0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_uitofp_i64(i64 %a) #0 {
|
||||
%r = uitofp i64 %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_sitofp_i32:
|
||||
; CHECK-NEXT: scvtf s0, w0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_sitofp_i32(i32 %a) #0 {
|
||||
%r = sitofp i32 %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_sitofp_i64:
|
||||
; CHECK-NEXT: scvtf s0, x0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_sitofp_i64(i64 %a) #0 {
|
||||
%r = sitofp i64 %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fptrunc_float:
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
define half @test_fptrunc_float(float %a) #0 {
|
||||
%r = fptrunc float %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fptrunc_double:
|
||||
; CHECK-NEXT: fcvt h0, d0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_fptrunc_double(double %a) #0 {
|
||||
%r = fptrunc double %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fpext_float:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: ret
|
||||
define float @test_fpext_float(half %a) #0 {
|
||||
%r = fpext half %a to float
|
||||
ret float %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fpext_double:
|
||||
; CHECK-NEXT: fcvt d0, h0
|
||||
; CHECK-NEXT: ret
|
||||
define double @test_fpext_double(half %a) #0 {
|
||||
%r = fpext half %a to double
|
||||
ret double %r
|
||||
}
|
||||
|
||||
|
||||
; CHECK-LABEL: test_bitcast_halftoi16:
|
||||
; CHECK-NEXT: fmov w0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define i16 @test_bitcast_halftoi16(half %a) #0 {
|
||||
%r = bitcast half %a to i16
|
||||
ret i16 %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_bitcast_i16tohalf:
|
||||
; CHECK-NEXT: fmov s0, w0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_bitcast_i16tohalf(i16 %a) #0 {
|
||||
%r = bitcast i16 %a to half
|
||||
ret half %r
|
||||
}
|
||||
|
||||
|
||||
declare half @llvm.sqrt.f16(half %a) #0
|
||||
declare half @llvm.powi.f16(half %a, i32 %b) #0
|
||||
declare half @llvm.sin.f16(half %a) #0
|
||||
declare half @llvm.cos.f16(half %a) #0
|
||||
declare half @llvm.pow.f16(half %a, half %b) #0
|
||||
declare half @llvm.exp.f16(half %a) #0
|
||||
declare half @llvm.exp2.f16(half %a) #0
|
||||
declare half @llvm.log.f16(half %a) #0
|
||||
declare half @llvm.log10.f16(half %a) #0
|
||||
declare half @llvm.log2.f16(half %a) #0
|
||||
declare half @llvm.fma.f16(half %a, half %b, half %c) #0
|
||||
declare half @llvm.fabs.f16(half %a) #0
|
||||
declare half @llvm.minnum.f16(half %a, half %b) #0
|
||||
declare half @llvm.maxnum.f16(half %a, half %b) #0
|
||||
declare half @llvm.copysign.f16(half %a, half %b) #0
|
||||
declare half @llvm.floor.f16(half %a) #0
|
||||
declare half @llvm.ceil.f16(half %a) #0
|
||||
declare half @llvm.trunc.f16(half %a) #0
|
||||
declare half @llvm.rint.f16(half %a) #0
|
||||
declare half @llvm.nearbyint.f16(half %a) #0
|
||||
declare half @llvm.round.f16(half %a) #0
|
||||
declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
|
||||
|
||||
; CHECK-LABEL: test_sqrt:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fsqrt s0, s0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_sqrt(half %a) #0 {
|
||||
%r = call half @llvm.sqrt.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_powi:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}__powisf2
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_powi(half %a, i32 %b) #0 {
|
||||
%r = call half @llvm.powi.f16(half %a, i32 %b)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_sin:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}sinf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_sin(half %a) #0 {
|
||||
%r = call half @llvm.sin.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_cos:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}cosf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_cos(half %a) #0 {
|
||||
%r = call half @llvm.cos.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_pow:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: bl {{_?}}powf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_pow(half %a, half %b) #0 {
|
||||
%r = call half @llvm.pow.f16(half %a, half %b)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_exp:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}expf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_exp(half %a) #0 {
|
||||
%r = call half @llvm.exp.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_exp2:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}exp2f
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_exp2(half %a) #0 {
|
||||
%r = call half @llvm.exp2.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_log:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}logf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_log(half %a) #0 {
|
||||
%r = call half @llvm.log.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_log10:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}log10f
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_log10(half %a) #0 {
|
||||
%r = call half @llvm.log10.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_log2:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: bl {{_?}}log2f
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_log2(half %a) #0 {
|
||||
%r = call half @llvm.log2.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fma:
|
||||
; CHECK-NEXT: fcvt s2, h2
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fmadd s0, s0, s1, s2
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_fma(half %a, half %b, half %c) #0 {
|
||||
%r = call half @llvm.fma.f16(half %a, half %b, half %c)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fabs:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fabs s0, s0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_fabs(half %a) #0 {
|
||||
%r = call half @llvm.fabs.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_minnum:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: bl {{_?}}fminf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_minnum(half %a, half %b) #0 {
|
||||
%r = call half @llvm.minnum.f16(half %a, half %b)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_maxnum:
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #-16]!
|
||||
; CHECK-NEXT: mov x29, sp
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: bl {{_?}}fmaxf
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ldp x29, x30, [sp], #16
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_maxnum(half %a, half %b) #0 {
|
||||
%r = call half @llvm.maxnum.f16(half %a, half %b)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_copysign:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: movi.4s v2, #0x80, lsl #24
|
||||
; CHECK-NEXT: bit.16b v0, v1, v2
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_copysign(half %a, half %b) #0 {
|
||||
%r = call half @llvm.copysign.f16(half %a, half %b)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_floor:
|
||||
; CHECK-NEXT: fcvt s1, h0
|
||||
; CHECK-NEXT: frintm s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: frintx s1, s1
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_floor(half %a) #0 {
|
||||
%r = call half @llvm.floor.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_ceil:
|
||||
; CHECK-NEXT: fcvt s1, h0
|
||||
; CHECK-NEXT: frintp s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: frintx s1, s1
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_ceil(half %a) #0 {
|
||||
%r = call half @llvm.ceil.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_trunc:
|
||||
; CHECK-NEXT: fcvt s1, h0
|
||||
; CHECK-NEXT: frintz s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: frintx s1, s1
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_trunc(half %a) #0 {
|
||||
%r = call half @llvm.trunc.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_rint:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: frintx s0, s0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_rint(half %a) #0 {
|
||||
%r = call half @llvm.rint.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_nearbyint:
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: frinti s0, s0
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_nearbyint(half %a) #0 {
|
||||
%r = call half @llvm.nearbyint.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_round:
|
||||
; CHECK-NEXT: fcvt s1, h0
|
||||
; CHECK-NEXT: frinta s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: frintx s1, s1
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_round(half %a) #0 {
|
||||
%r = call half @llvm.round.f16(half %a)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_fmuladd:
|
||||
; CHECK-NEXT: fcvt s1, h1
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fmul s0, s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: fcvt s0, h0
|
||||
; CHECK-NEXT: fcvt s1, h2
|
||||
; CHECK-NEXT: fadd s0, s0, s1
|
||||
; CHECK-NEXT: fcvt h0, s0
|
||||
; CHECK-NEXT: ret
|
||||
define half @test_fmuladd(half %a, half %b, half %c) #0 {
|
||||
%r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
|
||||
ret half %r
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
@ -1,109 +0,0 @@
|
||||
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
|
||||
|
||||
define half @add_h(half %a, half %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: add_h:
|
||||
; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
|
||||
; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
|
||||
; CHECK: fadd [[RES:s[0-9]+]], [[OP1]], [[OP2]]
|
||||
; CHECK: fcvt h0, [[RES]]
|
||||
%0 = fadd half %a, %b
|
||||
ret half %0
|
||||
}
|
||||
|
||||
|
||||
define half @sub_h(half %a, half %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: sub_h:
|
||||
; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
|
||||
; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
|
||||
; CHECK: fsub [[RES:s[0-9]+]], [[OP1]], [[OP2]]
|
||||
; CHECK: fcvt h0, [[RES]]
|
||||
%0 = fsub half %a, %b
|
||||
ret half %0
|
||||
}
|
||||
|
||||
|
||||
define half @mul_h(half %a, half %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: mul_h:
|
||||
; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
|
||||
; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
|
||||
; CHECK: fmul [[RES:s[0-9]+]], [[OP1]], [[OP2]]
|
||||
; CHECK: fcvt h0, [[RES]]
|
||||
%0 = fmul half %a, %b
|
||||
ret half %0
|
||||
}
|
||||
|
||||
|
||||
define half @div_h(half %a, half %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: div_h:
|
||||
; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0
|
||||
; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1
|
||||
; CHECK: fdiv [[RES:s[0-9]+]], [[OP1]], [[OP2]]
|
||||
; CHECK: fcvt h0, [[RES]]
|
||||
%0 = fdiv half %a, %b
|
||||
ret half %0
|
||||
}
|
||||
|
||||
|
||||
define half @load_h(half* %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: load_h:
|
||||
; CHECK: ldr h0, [x0]
|
||||
%0 = load half, half* %a, align 4
|
||||
ret half %0
|
||||
}
|
||||
|
||||
|
||||
define void @store_h(half* %a, half %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: store_h:
|
||||
; CHECK: str h0, [x0]
|
||||
store half %b, half* %a, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define half @s_to_h(float %a) {
|
||||
; CHECK-LABEL: s_to_h:
|
||||
; CHECK: fcvt h0, s0
|
||||
%1 = fptrunc float %a to half
|
||||
ret half %1
|
||||
}
|
||||
|
||||
define half @d_to_h(double %a) {
|
||||
; CHECK-LABEL: d_to_h:
|
||||
; CHECK: fcvt h0, d0
|
||||
%1 = fptrunc double %a to half
|
||||
ret half %1
|
||||
}
|
||||
|
||||
define float @h_to_s(half %a) {
|
||||
; CHECK-LABEL: h_to_s:
|
||||
; CHECK: fcvt s0, h0
|
||||
%1 = fpext half %a to float
|
||||
ret float %1
|
||||
}
|
||||
|
||||
define double @h_to_d(half %a) {
|
||||
; CHECK-LABEL: h_to_d:
|
||||
; CHECK: fcvt d0, h0
|
||||
%1 = fpext half %a to double
|
||||
ret double %1
|
||||
}
|
||||
|
||||
define half @bitcast_i_to_h(i16 %a) {
|
||||
; CHECK-LABEL: bitcast_i_to_h:
|
||||
; CHECK: fmov s0, w0
|
||||
%1 = bitcast i16 %a to half
|
||||
ret half %1
|
||||
}
|
||||
|
||||
|
||||
define i16 @bitcast_h_to_i(half %a) {
|
||||
; CHECK-LABEL: bitcast_h_to_i:
|
||||
; CHECK: fmov w0, s0
|
||||
%1 = bitcast half %a to i16
|
||||
ret i16 %1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user