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[CodeGen][SelectionDAG]Add new intrinsic experimental.vector.reverse
This patch adds a new intrinsic experimental.vector.reduce that takes a single vector and returns a vector of matching type but with the original lane order reversed. For example: ``` vector.reverse(<A,B,C,D>) ==> <D,C,B,A> ``` The new intrinsic supports fixed and scalable vectors types. The fixed-width vector relies on shufflevector to maintain existing behaviour. Scalable vector uses the new ISD node - VECTOR_REVERSE. This new intrinsic is one of the named shufflevector intrinsics proposed on the mailing-list in the RFC at [1]. Patch by Paul Walker (@paulwalker-arm). [1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html Differential Revision: https://reviews.llvm.org/D94883
This commit is contained in:
Caroline Concatto
parent
b6252362a0
commit
9ea32f75fa
@ -16233,6 +16233,33 @@ runtime, then the result vector is undefined. The ``idx`` parameter must be a
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vector index constant type (for most targets this will be an integer pointer
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type).
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'``llvm.experimental.vector.reverse``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
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declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
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Overview:
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"""""""""
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The '``llvm.experimental.vector.reverse.*``' intrinsics reverse a vector.
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The intrinsic takes a single vector and returns a vector of matching type but
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with the original lane order reversed. These intrinsics work for both fixed
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and scalable vectors. While this intrinsic is marked as experimental the
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recommended way to express reverse operations for fixed-width vectors is still
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to use a shufflevector, as that may allow for more optimization opportunities.
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Arguments:
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""""""""""
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The argument to this intrinsic must be a vector.
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Matrix Intrinsics
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-----------------
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@ -540,6 +540,11 @@ enum NodeType {
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/// vector, but not the other way around.
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EXTRACT_SUBVECTOR,
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/// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
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/// whose elements are shuffled using the following algorithm:
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/// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
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VECTOR_REVERSE,
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/// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
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/// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
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/// values that indicate which value (or undef) each result element will
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@ -1635,6 +1635,12 @@ def int_preserve_struct_access_index : DefaultAttrsIntrinsic<[llvm_anyptr_ty],
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ImmArg<ArgIndex<1>>,
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ImmArg<ArgIndex<2>>]>;
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//===------------ Intrinsics to perform common vector shuffles ------------===//
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def int_experimental_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem]>;
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//===---------- Intrinsics to query properties of scalable vectors --------===//
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def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>;
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@ -254,6 +254,9 @@ def SDTFPVecReduce : SDTypeProfile<1, 1, [ // FP vector reduction
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SDTCisFP<0>, SDTCisVec<1>
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]>;
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def SDTVecReverse : SDTypeProfile<1, 1, [ // vector reverse
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SDTCisVec<0>, SDTCisSameAs<0,1>
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]>;
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def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
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SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
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@ -651,6 +654,7 @@ def ist : SDNode<"ISD::STORE" , SDTIStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
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def vector_reverse : SDNode<"ISD::VECTOR_REVERSE", SDTVecReverse>;
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def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
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def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
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def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
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@ -5373,6 +5373,12 @@ static Value *simplifyUnaryIntrinsic(Function *F, Value *Op0,
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return Op0;
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break;
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}
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case Intrinsic::experimental_vector_reverse:
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// experimental.vector.reverse(experimental.vector.reverse(x)) -> x
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if (match(Op0,
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m_Intrinsic<Intrinsic::experimental_vector_reverse>(m_Value(X))))
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return X;
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break;
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default:
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break;
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}
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@ -96,6 +96,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
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case ISD::EXTRACT_SUBVECTOR:
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Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
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case ISD::VECTOR_REVERSE:
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Res = PromoteIntRes_VECTOR_REVERSE(N); break;
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case ISD::VECTOR_SHUFFLE:
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Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
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case ISD::INSERT_VECTOR_ELT:
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@ -4662,6 +4664,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
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return DAG.getBuildVector(NOutVT, dl, Ops);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
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SDLoc dl(N);
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SDValue V0 = GetPromotedInteger(N->getOperand(0));
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EVT OutVT = V0.getValueType();
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return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0);
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
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ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
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@ -298,6 +298,7 @@ private:
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SDValue PromoteIntRes_Atomic1(AtomicSDNode *N);
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SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
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SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N);
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SDValue PromoteIntRes_VECTOR_REVERSE(SDNode *N);
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SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
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SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
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SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
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@ -834,6 +835,7 @@ private:
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void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_ScalarOp(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
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SDValue &Hi);
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void SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi);
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@ -930,6 +930,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::SETCC:
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SplitVecRes_SETCC(N, Lo, Hi);
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break;
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case ISD::VECTOR_REVERSE:
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SplitVecRes_VECTOR_REVERSE(N, Lo, Hi);
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break;
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case ISD::VECTOR_SHUFFLE:
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
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break;
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@ -5492,3 +5495,13 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
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Ops[Idx] = FillVal;
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return DAG.getBuildVector(NVT, dl, Ops);
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}
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void DAGTypeLegalizer::SplitVecRes_VECTOR_REVERSE(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue InLo, InHi;
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GetSplitVector(N->getOperand(0), InLo, InHi);
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SDLoc DL(N);
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Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, InHi.getValueType(), InHi);
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Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, InLo.getValueType(), InLo);
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}
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@ -7025,6 +7025,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index));
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return;
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}
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case Intrinsic::experimental_vector_reverse:
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visitVectorReverse(I);
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return;
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}
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}
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@ -10836,6 +10839,29 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
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}
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}
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void SelectionDAGBuilder::visitVectorReverse(const CallInst &I) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
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SDLoc DL = getCurSDLoc();
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SDValue V = getValue(I.getOperand(0));
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assert(VT == V.getValueType() && "Malformed vector.reverse!");
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if (VT.isScalableVector()) {
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setValue(&I, DAG.getNode(ISD::VECTOR_REVERSE, DL, VT, V));
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return;
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}
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// Use VECTOR_SHUFFLE for the fixed-length vector
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// to maintain existing behavior.
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SmallVector<int, 8> Mask;
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unsigned NumElts = VT.getVectorMinNumElements();
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for (unsigned i = 0; i != NumElts; ++i)
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Mask.push_back(NumElts - 1 - i);
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setValue(&I, DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), Mask));
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}
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void SelectionDAGBuilder::visitFreeze(const FreezeInst &I) {
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
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@ -773,6 +773,7 @@ private:
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void visitGCResult(const GCResultInst &I);
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void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
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void visitVectorReverse(const CallInst &I);
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void visitUserOp1(const Instruction &I) {
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llvm_unreachable("UserOp1 should not exist at instruction selection time!");
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@ -289,6 +289,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::SCALAR_TO_VECTOR: return "scalar_to_vector";
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case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
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case ISD::SPLAT_VECTOR: return "splat_vector";
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case ISD::VECTOR_REVERSE: return "vector_reverse";
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case ISD::CARRY_FALSE: return "carry_false";
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case ISD::ADDC: return "addc";
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case ISD::ADDE: return "adde";
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@ -3894,7 +3894,7 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
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return false;
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// Vectors (of > 1 lane) in big endian need tricky handling.
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if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
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if (RVEVT.isVector() && RVEVT.getVectorElementCount().isVector() &&
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!Subtarget->isLittleEndian())
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return false;
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@ -1853,7 +1853,6 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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MAKE_CASE(AArch64ISD::CLASTB_N)
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MAKE_CASE(AArch64ISD::LASTA)
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MAKE_CASE(AArch64ISD::LASTB)
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MAKE_CASE(AArch64ISD::REV)
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MAKE_CASE(AArch64ISD::REINTERPRET_CAST)
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MAKE_CASE(AArch64ISD::TBL)
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MAKE_CASE(AArch64ISD::FADD_PRED)
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@ -3594,7 +3593,7 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getNode(AArch64ISD::LASTB, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::aarch64_sve_rev:
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return DAG.getNode(AArch64ISD::REV, dl, Op.getValueType(),
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return DAG.getNode(ISD::VECTOR_REVERSE, dl, Op.getValueType(),
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Op.getOperand(1));
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case Intrinsic::aarch64_sve_tbl:
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return DAG.getNode(AArch64ISD::TBL, dl, Op.getValueType(),
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@ -292,7 +292,6 @@ enum NodeType : unsigned {
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CLASTB_N,
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LASTA,
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LASTB,
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REV,
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TBL,
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// Floating-point reductions.
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@ -249,9 +249,6 @@ def AArch64clasta_n : SDNode<"AArch64ISD::CLASTA_N", SDT_AArch64ReduceWithIn
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def AArch64clastb_n : SDNode<"AArch64ISD::CLASTB_N", SDT_AArch64ReduceWithInit>;
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def AArch64fadda_p : SDNode<"AArch64ISD::FADDA_PRED", SDT_AArch64ReduceWithInit>;
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def SDT_AArch64Rev : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
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def AArch64rev : SDNode<"AArch64ISD::REV", SDT_AArch64Rev>;
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def SDT_AArch64PTest : SDTypeProfile<0, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
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def AArch64ptest : SDNode<"AArch64ISD::PTEST", SDT_AArch64PTest>;
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@ -587,8 +584,8 @@ let Predicates = [HasSVE] in {
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defm REVH_ZPmZ : sve_int_perm_rev_revh<"revh", int_aarch64_sve_revh>;
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defm REVW_ZPmZ : sve_int_perm_rev_revw<"revw", int_aarch64_sve_revw>;
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defm REV_PP : sve_int_perm_reverse_p<"rev", AArch64rev>;
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defm REV_ZZ : sve_int_perm_reverse_z<"rev", AArch64rev>;
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defm REV_PP : sve_int_perm_reverse_p<"rev", vector_reverse>;
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defm REV_ZZ : sve_int_perm_reverse_z<"rev", vector_reverse>;
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defm SUNPKLO_ZZ : sve_int_perm_unpk<0b00, "sunpklo", AArch64sunpklo>;
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defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi", AArch64sunpkhi>;
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230
test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
Normal file
230
test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
Normal file
@ -0,0 +1,230 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SELDAG %s
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; RUN: llc -verify-machineinstrs -O0 < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FASTISEL %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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target triple = "aarch64-unknown-linux-gnu"
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;
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; VECTOR_REVERSE
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;
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define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
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; CHECK-LABEL: .LCPI0_0:
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; CHECK: .byte 15 // 0xf
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; CHECK-NEXT: .byte 14 // 0xe
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; CHECK-NEXT: .byte 13 // 0xd
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; CHECK-NEXT: .byte 12 // 0xc
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; CHECK-NEXT: .byte 11 // 0xb
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; CHECK-NEXT: .byte 10 // 0xa
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; CHECK-NEXT: .byte 9 // 0x9
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; CHECK-NEXT: .byte 8 // 0x8
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; CHECK-NEXT: .byte 7 // 0x7
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; CHECK-NEXT: .byte 6 // 0x6
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; CHECK-NEXT: .byte 5 // 0x5
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; CHECK-NEXT: .byte 4 // 0x4
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; CHECK-NEXT: .byte 3 // 0x3
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; CHECK-NEXT: .byte 2 // 0x2
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; CHECK-NEXT: .byte 1 // 0x1
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; CHECK-NEXT: .byte 0 // 0x0
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; CHECK-LABEL: reverse_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
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ret <16 x i8> %res
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}
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define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
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; CHECK-LABEL: .LCPI1_0:
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; CHECK: .byte 14 // 0xe
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; CHECK-NEXT: .byte 15 // 0xf
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; CHECK-NEXT: .byte 12 // 0xc
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; CHECK-NEXT: .byte 13 // 0xd
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; CHECK-NEXT: .byte 10 // 0xa
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; CHECK-NEXT: .byte 11 // 0xb
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; CHECK-NEXT: .byte 8 // 0x8
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; CHECK-NEXT: .byte 9 // 0x9
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; CHECK-NEXT: .byte 6 // 0x6
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; CHECK-NEXT: .byte 7 // 0x7
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; CHECK-NEXT: .byte 4 // 0x4
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; CHECK-NEXT: .byte 5 // 0x5
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; CHECK-NEXT: .byte 2 // 0x2
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; CHECK-NEXT: .byte 3 // 0x3
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; CHECK-NEXT: .byte 0 // 0x0
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; CHECK-NEXT: .byte 1 // 0x1
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; CHECK-LABEL: reverse_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
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; CHECK-NEXT: ret
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%res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
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ret <8 x i16> %res
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}
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define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: reverse_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev64 v0.4s, v0.4s
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
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ret <4 x i32> %res
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}
|
||||
|
||||
define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
|
||||
ret <2 x i64> %res
|
||||
}
|
||||
|
||||
define <8 x half> @reverse_v8f16(<8 x half> %a) #0 {
|
||||
; CHECK-LABEL: .LCPI4_0:
|
||||
; CHECK: .byte 14 // 0xe
|
||||
; CHECK-NEXT: .byte 15 // 0xf
|
||||
; CHECK-NEXT: .byte 12 // 0xc
|
||||
; CHECK-NEXT: .byte 13 // 0xd
|
||||
; CHECK-NEXT: .byte 10 // 0xa
|
||||
; CHECK-NEXT: .byte 11 // 0xb
|
||||
; CHECK-NEXT: .byte 8 // 0x8
|
||||
; CHECK-NEXT: .byte 9 // 0x9
|
||||
; CHECK-NEXT: .byte 6 // 0x6
|
||||
; CHECK-NEXT: .byte 7 // 0x7
|
||||
; CHECK-NEXT: .byte 4 // 0x4
|
||||
; CHECK-NEXT: .byte 5 // 0x5
|
||||
; CHECK-NEXT: .byte 2 // 0x2
|
||||
; CHECK-NEXT: .byte 3 // 0x3
|
||||
; CHECK-NEXT: .byte 0 // 0x0
|
||||
; CHECK-NEXT: .byte 1 // 0x1
|
||||
; CHECK-LABEL: reverse_v8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: adrp x8, .LCPI4_0
|
||||
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
|
||||
; CHECK-NEXT: tbl v0.16b, { v0.16b }, v1.16b
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a)
|
||||
ret <8 x half> %res
|
||||
}
|
||||
|
||||
define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev64 v0.4s, v0.4s
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
; Verify promote type legalisation works as expected.
|
||||
define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev64 v0.2s, v0.2s
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
|
||||
ret <2 x i8> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v8i32:
|
||||
; CHECK-SELDAG: // %bb.0:
|
||||
; CHECK-SELDAG-NEXT: rev64 v1.4s, v1.4s
|
||||
; CHECK-SELDAG-NEXT: rev64 v2.4s, v0.4s
|
||||
; CHECK-SELDAG-NEXT: ext v0.16b, v1.16b, v1.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ret
|
||||
; CHECK-FASTISEL: // %bb.0:
|
||||
; CHECK-FASTISEL-NEXT: sub sp, sp, #16
|
||||
; CHECK-FASTISEL-NEXT: str q1, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov v1.16b, v0.16b
|
||||
; CHECK-FASTISEL-NEXT: ldr q0, [sp]
|
||||
; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: add sp, sp, #16
|
||||
; CHECK-FASTISEL-NEXT: ret
|
||||
|
||||
%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v16f32:
|
||||
; CHECK-SELDAG: // %bb.0:
|
||||
; CHECK-SELDAG-NEXT: rev64 v3.4s, v3.4s
|
||||
; CHECK-SELDAG-NEXT: rev64 v2.4s, v2.4s
|
||||
; CHECK-SELDAG-NEXT: rev64 v4.4s, v1.4s
|
||||
; CHECK-SELDAG-NEXT: rev64 v5.4s, v0.4s
|
||||
; CHECK-SELDAG-NEXT: ext v0.16b, v3.16b, v3.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ext v1.16b, v2.16b, v2.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ext v2.16b, v4.16b, v4.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ext v3.16b, v5.16b, v5.16b, #8
|
||||
; CHECK-SELDAG-NEXT: ret
|
||||
; CHECK-FASTISEL: // %bb.0:
|
||||
; CHECK-FASTISEL-NEXT: sub sp, sp, #32
|
||||
; CHECK-FASTISEL-NEXT: str q3, [sp, #16]
|
||||
; CHECK-FASTISEL-NEXT: str q2, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov v2.16b, v1.16b
|
||||
; CHECK-FASTISEL-NEXT: ldr q1, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov v3.16b, v0.16b
|
||||
; CHECK-FASTISEL-NEXT: ldr q0, [sp, #16]
|
||||
; CHECK-FASTISEL-NEXT: rev64 v0.4s, v0.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: rev64 v1.4s, v1.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: rev64 v2.4s, v2.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: rev64 v3.4s, v3.4s
|
||||
; CHECK-FASTISEL-NEXT: ext v3.16b, v3.16b, v3.16b, #8
|
||||
; CHECK-FASTISEL-NEXT: add sp, sp, #32
|
||||
; CHECK-FASTISEL-NEXT: ret
|
||||
|
||||
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
|
||||
declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
|
||||
declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
|
||||
declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
|
||||
declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
|
||||
declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
|
||||
declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
|
||||
declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
|
||||
declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
|
||||
declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
|
||||
declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
|
||||
|
||||
attributes #0 = { nounwind "target-features"="+neon" }
|
||||
238
test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
Normal file
238
test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
Normal file
@ -0,0 +1,238 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SELDAG %s
|
||||
; RUN: llc -verify-machineinstrs -O0 < %s 2>%t | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FASTISEL %s
|
||||
|
||||
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
|
||||
|
||||
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
|
||||
; WARN-NOT: warning
|
||||
|
||||
target triple = "aarch64-unknown-linux-gnu"
|
||||
|
||||
;
|
||||
; VECTOR_REVERSE - PPR
|
||||
;
|
||||
|
||||
define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv2i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev p0.d, p0.d
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
|
||||
ret <vscale x 2 x i1> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv4i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev p0.s, p0.s
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
|
||||
ret <vscale x 4 x i1> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv8i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev p0.h, p0.h
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
|
||||
ret <vscale x 8 x i1> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv16i1:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev p0.b, p0.b
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
|
||||
ret <vscale x 16 x i1> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv32i1:
|
||||
; CHECK-SELDAG: // %bb.0:
|
||||
; CHECK-SELDAG-NEXT: rev p2.b, p1.b
|
||||
; CHECK-SELDAG-NEXT: rev p1.b, p0.b
|
||||
; CHECK-SELDAG-NEXT: mov p0.b, p2.b
|
||||
; CHECK-SELDAG-NEXT: ret
|
||||
; CHECK-FASTISEL: // %bb.0:
|
||||
; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-FASTISEL-NEXT: str p1, [sp, #7, mul vl]
|
||||
; CHECK-FASTISEL-NEXT: mov p1.b, p0.b
|
||||
; CHECK-FASTISEL-NEXT: ldr p0, [sp, #7, mul vl]
|
||||
; CHECK-FASTISEL-NEXT: rev p0.b, p0.b
|
||||
; CHECK-FASTISEL-NEXT: rev p1.b, p1.b
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #1
|
||||
; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
|
||||
; CHECK-FASTISEL-NEXT: ret
|
||||
|
||||
%res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
|
||||
ret <vscale x 32 x i1> %res
|
||||
}
|
||||
|
||||
;
|
||||
; VECTOR_REVERSE - ZPR
|
||||
;
|
||||
|
||||
define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.b, z0.b
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv8f16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a)
|
||||
ret <vscale x 8 x half> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv4f32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a) ret <vscale x 4 x float> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv2f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
|
||||
ret <vscale x 2 x double> %res
|
||||
}
|
||||
|
||||
; Verify promote type legalisation works as expected.
|
||||
define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv2i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: rev z0.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
|
||||
%res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)
|
||||
ret <vscale x 2 x i8> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv8i32:
|
||||
; CHECK-SELDAG: // %bb.0:
|
||||
; CHECK-SELDAG-NEXT: rev z2.s, z1.s
|
||||
; CHECK-SELDAG-NEXT: rev z1.s, z0.s
|
||||
; CHECK-SELDAG-NEXT: mov z0.d, z2.d
|
||||
; CHECK-SELDAG-NEXT: ret
|
||||
; CHECK-FASTISEL: // %bb.0:
|
||||
; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-FASTISEL-NEXT: str z1, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov z1.d, z0.d
|
||||
; CHECK-FASTISEL-NEXT: ldr z0, [sp]
|
||||
; CHECK-FASTISEL-NEXT: rev z0.s, z0.s
|
||||
; CHECK-FASTISEL-NEXT: rev z1.s, z1.s
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #1
|
||||
; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
|
||||
; CHECK-FASTISEL-NEXT: ret
|
||||
|
||||
%res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
|
||||
ret <vscale x 8 x i32> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_nxv16f32:
|
||||
; CHECK-SELDAG: // %bb.0:
|
||||
; CHECK-SELDAG-NEXT: rev z5.s, z3.s
|
||||
; CHECK-SELDAG-NEXT: rev z4.s, z2.s
|
||||
; CHECK-SELDAG-NEXT: rev z2.s, z1.s
|
||||
; CHECK-SELDAG-NEXT: rev z3.s, z0.s
|
||||
; CHECK-SELDAG-NEXT: mov z0.d, z5.d
|
||||
; CHECK-SELDAG-NEXT: mov z1.d, z4.d
|
||||
; CHECK-SELDAG-NEXT: ret
|
||||
; CHECK-FASTISEL: // %bb.0:
|
||||
; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #-2
|
||||
; CHECK-FASTISEL-NEXT: str z3, [sp, #1, mul vl]
|
||||
; CHECK-FASTISEL-NEXT: str z2, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov z2.d, z1.d
|
||||
; CHECK-FASTISEL-NEXT: ldr z1, [sp]
|
||||
; CHECK-FASTISEL-NEXT: mov z3.d, z0.d
|
||||
; CHECK-FASTISEL-NEXT: ldr z0, [sp, #1, mul vl]
|
||||
; CHECK-FASTISEL-NEXT: rev z0.s, z0.s
|
||||
; CHECK-FASTISEL-NEXT: rev z1.s, z1.s
|
||||
; CHECK-FASTISEL-NEXT: rev z2.s, z2.s
|
||||
; CHECK-FASTISEL-NEXT: rev z3.s, z3.s
|
||||
; CHECK-FASTISEL-NEXT: addvl sp, sp, #2
|
||||
; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
|
||||
; CHECK-FASTISEL-NEXT: ret
|
||||
|
||||
%res = call <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float> %a)
|
||||
ret <vscale x 16 x float> %res
|
||||
}
|
||||
|
||||
|
||||
declare <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1>)
|
||||
declare <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1>)
|
||||
declare <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1>)
|
||||
declare <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1>)
|
||||
declare <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1>)
|
||||
declare <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8>)
|
||||
declare <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64>)
|
||||
declare <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half>)
|
||||
declare <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float>)
|
||||
declare <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float>)
|
||||
declare <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double>)
|
||||
|
||||
|
||||
attributes #0 = { nounwind "target-features"="+sve" }
|
||||
139
test/CodeGen/X86/named-vector-shuffle-reverse.ll
Normal file
139
test/CodeGen/X86/named-vector-shuffle-reverse.ll
Normal file
@ -0,0 +1,139 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -verify-machineinstrs < %s 2>%t | FileCheck %s
|
||||
|
||||
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
|
||||
|
||||
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
|
||||
; WARN-NOT: warning
|
||||
|
||||
|
||||
target triple = "x86_64-unknown-unknown"
|
||||
|
||||
;
|
||||
; VECTOR_REVERSE
|
||||
;
|
||||
|
||||
define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v16i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-NEXT: punpcklbw %xmm1, %xmm
|
||||
; CHECK-NEXT: pshufd $78, %xmm2, %xmm2
|
||||
; CHECK-NEXT: pshuflw $27, %xmm2, %xmm2
|
||||
; CHECK-NEXT: pshufhw $27, %xmm2, %xmm2
|
||||
; CHECK-NEXT: punpckhbw %xmm1, %xmm0
|
||||
; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
|
||||
; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: packuswb %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a)
|
||||
ret <16 x i8> %res
|
||||
}
|
||||
|
||||
define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v8i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pshufd $78, %xmm0, %xmm
|
||||
; CHECK-NEXT: pshuflw $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: pshufhw $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a)
|
||||
ret <8 x i16> %res
|
||||
}
|
||||
|
||||
define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v4i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pshufd $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a)
|
||||
ret <4 x i32> %res
|
||||
}
|
||||
|
||||
define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pshufd $78, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
|
||||
ret <2 x i64> %res
|
||||
}
|
||||
|
||||
define <4 x float> @reverse_v4f32(<4 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v4f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: shufps $27, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a)
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <2 x double> @reverse_v2f64(<2 x double> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: shufps $78, %xmm0, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
; Verify promote type legalisation works as expected.
|
||||
define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v2i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movdqa %xmm0, %xmm1
|
||||
; CHECK-NEXT: psrlw $8, %xmm1
|
||||
; CHECK-NEXT: psllw $8, %xmm0
|
||||
; CHECK-NEXT: por %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
|
||||
ret <2 x i8> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v8i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: pshufd $27, %xmm1, %xmm2
|
||||
; CHECK-NEXT: pshufd $27, %xmm0, %xmm1
|
||||
; CHECK-NEXT: movdqa %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a)
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
; Verify splitvec type legalisation works as expected.
|
||||
define <16 x float> @reverse_v16f32(<16 x float> %a) #0 {
|
||||
; CHECK-LABEL: reverse_v16f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movaps %xmm1, %xmm4
|
||||
; CHECK-NEXT: movaps %xmm0, %xmm5
|
||||
; CHECK-NEXT: shufps $27, %xmm3, %xmm
|
||||
; CHECK-NEXT: shufps $27, %xmm2, %xmm2
|
||||
; CHECK-NEXT: shufps $27, %xmm1, %xmm4
|
||||
; CHECK-NEXT: shufps $27, %xmm0, %xmm5
|
||||
; CHECK-NEXT: movaps %xmm3, %xmm0
|
||||
; CHECK-NEXT: movaps %xmm2, %xmm1
|
||||
; CHECK-NEXT: movaps %xmm4, %xmm2
|
||||
; CHECK-NEXT: movaps %xmm5, %xmm3
|
||||
|
||||
%res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a)
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
|
||||
declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>)
|
||||
declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>)
|
||||
declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>)
|
||||
declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>)
|
||||
declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>)
|
||||
declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>)
|
||||
declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>)
|
||||
declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>)
|
||||
declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>)
|
||||
declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>)
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
17
test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll
Normal file
17
test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll
Normal file
@ -0,0 +1,17 @@
|
||||
; RUN: opt -instsimplify -S < %s 2>%t | FileCheck %s
|
||||
|
||||
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
|
||||
|
||||
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
|
||||
; WARN-NOT: warning
|
||||
|
||||
; Test back to back reverse shuffles are eliminated.
|
||||
define <vscale x 4 x i32> @shuffle_b2b_reverse(<vscale x 4 x i32> %a) {
|
||||
; CHECK-LABEL: @shuffle_b2b_reverse(
|
||||
; CHECK: ret <vscale x 4 x i32> %a
|
||||
%rev = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
|
||||
%rev.rev = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %rev)
|
||||
ret <vscale x 4 x i32> %rev.rev
|
||||
}
|
||||
|
||||
declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)
|
||||
Loading…
Reference in New Issue
Block a user