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[ARM] Expand ROTL and ROTR of vector value types

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Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection.

Reviewers: rengolin, t.p.northover

Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14082

llvm-svn: 251401
This commit is contained in:
Charlie Turner 2015-10-27 10:25:20 +00:00
parent 5eb276336b
commit 9ea464365e
4 changed files with 37 additions and 1 deletions
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4
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -220,6 +220,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
// AArch64 lacks both left-rotate and popcount instructions.
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i64, Expand);
for (MVT VT : MVT::vector_valuetypes()) {
setOperationAction(ISD::ROTL, VT, Expand);
setOperationAction(ISD::ROTR, VT, Expand);
}
// AArch64 doesn't have {U|S}MUL_LOHI.
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);

6
lib/Target/ARM/ARMISelLowering.cpp
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@ -718,7 +718,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
}
// ARM does not have ROTL.
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
for (MVT VT : MVT::vector_valuetypes()) {
setOperationAction(ISD::ROTL, VT, Expand);
setOperationAction(ISD::ROTR, VT, Expand);
}
setOperationAction(ISD::CTTZ, MVT::i32, Custom);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())

14
test/CodeGen/AArch64/rotate.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -mtriple=aarch64--linux-gnueabihf | FileCheck %s
;; This used to cause a backend crash about not being able to
;; select ROTL. Make sure if generates the basic ushr/shl.
define <2 x i64> @testcase(<2 x i64>* %in) {
; CHECK-LABEL: testcase
; CHECK: ushr {{v[0-9]+}}.2d
; CHECK: shl {{v[0-9]+}}.2d
%1 = load <2 x i64>, <2 x i64>* %in
%2 = lshr <2 x i64> %1, <i64 8, i64 8>
%3 = shl <2 x i64> %1, <i64 56, i64 56>
%4 = or <2 x i64> %2, %3
ret <2 x i64> %4
}

14
test/CodeGen/ARM/rotate.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s
;; This used to cause a backend crash about not being able to
;; select ROTL. Make sure if generates the basic VSHL/VSHR.
define <2 x i64> @testcase(<2 x i64>* %in) {
; CHECK-LABEL: testcase
; CHECK: vshl.i64
; CHECK: vshr.u64
%1 = load <2 x i64>, <2 x i64>* %in
%2 = lshr <2 x i64> %1, <i64 8, i64 8>
%3 = shl <2 x i64> %1, <i64 56, i64 56>
%4 = or <2 x i64> %2, %3
ret <2 x i64> %4
}