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[AMDGPU] Tidy SReg/SGPR definitions using template class
Use a multiclass to consistently define SReg/SGPR/TTMP register classes. Add missing TTMP registers for 96b, 160b, 192b, 224b. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D105800
This commit is contained in:
Carl Ritson
parent
54c34b405b
commit
9ee7bab63e
@ -373,6 +373,7 @@ def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
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let isAllocatable = 0;
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}
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// Trap handler TMP 16-bit registers
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def TTMP_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16,
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(add (sequence "TTMP%u_LO16", 0, 15))> {
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let Size = 16;
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@ -382,11 +383,25 @@ def TTMP_LO16 : RegisterClass<"AMDGPU", [i16, f16], 16,
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// Trap handler TMP 64-bit registers
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def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;
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// Trap handler TMP 96-bit registers
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def TTMP_96Regs : SIRegisterTuples<getSubRegs<3>.ret, TTMP_32, 15, 3, 3, "ttmp">;
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// Trap handler TMP 128-bit registers
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def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">;
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// Trap handler TMP 160-bit registers
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def TTMP_160Regs : SIRegisterTuples<getSubRegs<5>.ret, TTMP_32, 15, 4, 5, "ttmp">;
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// Trap handler TMP 192-bit registers
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def TTMP_192Regs : SIRegisterTuples<getSubRegs<6>.ret, TTMP_32, 15, 4, 6, "ttmp">;
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// Trap handler TMP 224-bit registers
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def TTMP_224Regs : SIRegisterTuples<getSubRegs<7>.ret, TTMP_32, 15, 4, 7, "ttmp">;
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// Trap handler TMP 256-bit registers
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def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">;
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// Trap handler TMP 512-bit registers
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def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">;
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class TmpRegTuplesBase<int index, int size,
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@ -693,130 +708,51 @@ def SReg_1 : RegisterClass<"AMDGPU", [i1], 32,
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let isAllocatable = 0;
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}
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// Requires 2 s_mov_b64 to copy
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let CopyCost = 2 in {
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multiclass SRegClass<int numRegs, int priority,
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list<ValueType> regTypes,
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SIRegisterTuples regList,
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SIRegisterTuples ttmpList = regList,
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int copyCost = !sra(!add(numRegs, 1), 1)> {
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defvar hasTTMP = !ne(regList, ttmpList);
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defvar suffix = !cast<string>(!mul(numRegs, 32));
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defvar sgprName = !strconcat("SGPR_", suffix);
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defvar ttmpName = !strconcat("TTMP_", suffix);
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// There are no 3-component scalar instructions, but this is needed
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// for symmetry with VGPRs.
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def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
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(add SGPR_96Regs)> {
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let AllocationPriority = 14;
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let AllocationPriority = priority, CopyCost = copyCost in {
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def "" # sgprName : RegisterClass<"AMDGPU", regTypes, 32, (add regList)> {
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}
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if hasTTMP then {
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def "" # ttmpName : RegisterClass<"AMDGPU", regTypes, 32, (add ttmpList)> {
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let isAllocatable = 0;
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}
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}
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def SReg_ # suffix :
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RegisterClass<"AMDGPU", regTypes, 32,
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!con(!dag(add, [!cast<RegisterClass>(sgprName)], ["sgpr"]),
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!if(hasTTMP,
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!dag(add, [!cast<RegisterClass>(ttmpName)], ["ttmp"]),
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(add)))> {
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let isAllocatable = 0;
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}
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}
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}
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def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
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(add SGPR_96)> {
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let AllocationPriority = 14;
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}
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def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
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(add SGPR_128Regs)> {
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let AllocationPriority = 15;
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}
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def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
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(add TTMP_128Regs)> {
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let isAllocatable = 0;
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}
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
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(add SGPR_128, TTMP_128)> {
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let isAllocatable = 0;
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}
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} // End CopyCost = 2
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// There are no 5-component scalar instructions, but this is needed
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// for symmetry with VGPRs.
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def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
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(add SGPR_160Regs)> {
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let AllocationPriority = 16;
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}
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def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
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(add SGPR_160)> {
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// FIXME: Should be isAllocatable = 0, but that causes all TableGen-generated
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// subclasses of SGPR_160 to be marked unallocatable too.
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// This occurs because SGPR_160 and SReg_160 classes are equivalent in size
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// meaning their enumeration order is dependent on alphanumeric ordering of
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// their names. The superclass for inherence is the last one in topological
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// order (i.e. enumeration order), hence SReg_160 is selected.
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// Potential workarounds involve renaming SGPR_160, adding another class
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// which is ordered last and hence used for inheritance, or adding more
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// registers to SReg_160 to cause it to be moved earlier in the superclass
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// list.
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let CopyCost = 3;
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}
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// There are no 6-component scalar instructions, but this is needed
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// for symmetry with VGPRs.
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def SGPR_192 : RegisterClass<"AMDGPU", [v6i32, v6f32, v3i64, v3f64], 32, (add SGPR_192Regs)> {
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let AllocationPriority = 17;
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}
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def SReg_192 : RegisterClass<"AMDGPU", [v6i32, v6f32, v3i64, v3f64], 32, (add SGPR_192)> {
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let isAllocatable = 0;
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let CopyCost = 3;
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}
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// There are no 7-component scalar instructions, but this is needed
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// for symmetry with VGPRs.
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def SGPR_224 : RegisterClass<"AMDGPU", [v7i32, v7f32], 32, (add SGPR_224Regs)> {
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let AllocationPriority = 18;
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}
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def SReg_224 : RegisterClass<"AMDGPU", [v7i32, v7f32], 32, (add SGPR_224)> {
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let isAllocatable = 0;
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let CopyCost = 4;
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}
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def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32, (add SGPR_256Regs)> {
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let AllocationPriority = 19;
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}
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def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32, (add TTMP_256Regs)> {
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let isAllocatable = 0;
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}
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def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64, v4f64], 32,
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(add SGPR_256, TTMP_256)> {
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// Requires 4 s_mov_b64 to copy
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let CopyCost = 4;
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let isAllocatable = 0;
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}
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def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32,
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(add SGPR_512Regs)> {
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let AllocationPriority = 20;
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}
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def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32,
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(add TTMP_512Regs)> {
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let isAllocatable = 0;
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}
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def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32, v8i64, v8f64], 32,
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(add SGPR_512, TTMP_512)> {
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// Requires 8 s_mov_b64 to copy
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let CopyCost = 8;
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let isAllocatable = 0;
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}
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defm "" : SRegClass<3, 14, [v3i32, v3f32], SGPR_96Regs, TTMP_96Regs>;
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defm "" : SRegClass<4, 15, [v4i32, v4f32, v2i64], SGPR_128Regs, TTMP_128Regs>;
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defm "" : SRegClass<5, 16, [v5i32, v5f32], SGPR_160Regs, TTMP_160Regs>;
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defm "" : SRegClass<6, 17, [v6i32, v6f32, v3i64, v3f64], SGPR_192Regs, TTMP_192Regs>;
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defm "" : SRegClass<7, 18, [v7i32, v7f32], SGPR_224Regs, TTMP_224Regs>;
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defm "" : SRegClass<8, 19, [v8i32, v8f32, v4i64, v4f64], SGPR_256Regs, TTMP_256Regs>;
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defm "" : SRegClass<16, 20, [v16i32, v16f32, v8i64, v8f64], SGPR_512Regs, TTMP_512Regs>;
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defm "" : SRegClass<32, 21, [v32i32, v32f32, v16i64, v16f64], SGPR_1024Regs>;
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def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add VGPR_32, LDS_DIRECT_CLASS)> {
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let isAllocatable = 0;
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}
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def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
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(add SGPR_1024Regs)> {
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let AllocationPriority = 21;
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}
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def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
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(add SGPR_1024)> {
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let CopyCost = 16;
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let isAllocatable = 0;
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}
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// Register class for all vector registers (VGPRs + Interpolation Registers)
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class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
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RegisterClass<"AMDGPU", regTypes, 32, regList> {
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@ -8,15 +8,15 @@
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define amdgpu_kernel void @s_input_output_i128() {
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; GFX908-LABEL: name: s_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4784138 /* regdef:SGPR_128 */, def %4
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 5111818 /* regdef:SGPR_128 */, def %4
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; GFX908: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:SGPR_128 */, [[COPY]]
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 5111817 /* reguse:SGPR_128 */, [[COPY]]
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; GFX908: S_ENDPGM 0
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; GFX90A-LABEL: name: s_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4784138 /* regdef:SGPR_128 */, def %4
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 5111818 /* regdef:SGPR_128 */, def %4
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; GFX90A: [[COPY:%[0-9]+]]:sgpr_128 = COPY %4
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:SGPR_128 */, [[COPY]]
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 5111817 /* reguse:SGPR_128 */, [[COPY]]
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; GFX90A: S_ENDPGM 0
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%val = tail call i128 asm sideeffect "; def $0", "=s"()
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call void asm sideeffect "; use $0", "s"(i128 %val)
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@ -26,15 +26,15 @@ define amdgpu_kernel void @s_input_output_i128() {
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define amdgpu_kernel void @v_input_output_i128() {
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; GFX908-LABEL: name: v_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4390922 /* regdef:VReg_128 */, def %4
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4718602 /* regdef:VReg_128 */, def %4
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; GFX908: [[COPY:%[0-9]+]]:vreg_128 = COPY %4
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4390921 /* reguse:VReg_128 */, [[COPY]]
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4718601 /* reguse:VReg_128 */, [[COPY]]
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; GFX908: S_ENDPGM 0
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; GFX90A-LABEL: name: v_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_128_Align2 */, def %4
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_128_Align2 */, def %4
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; GFX90A: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %4
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4521993 /* reguse:VReg_128_Align2 */, [[COPY]]
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4849673 /* reguse:VReg_128_Align2 */, [[COPY]]
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; GFX90A: S_ENDPGM 0
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%val = tail call i128 asm sideeffect "; def $0", "=v"()
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call void asm sideeffect "; use $0", "v"(i128 %val)
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@ -44,15 +44,15 @@ define amdgpu_kernel void @v_input_output_i128() {
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define amdgpu_kernel void @a_input_output_i128() {
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; GFX908-LABEL: name: a_input_output_i128
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; GFX908: bb.0 (%ir-block.0):
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4325386 /* regdef:AReg_128 */, def %4
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; GFX908: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4653066 /* regdef:AReg_128 */, def %4
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; GFX908: [[COPY:%[0-9]+]]:areg_128 = COPY %4
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4325385 /* reguse:AReg_128 */, [[COPY]]
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; GFX908: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4653065 /* reguse:AReg_128 */, [[COPY]]
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; GFX908: S_ENDPGM 0
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; GFX90A-LABEL: name: a_input_output_i128
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; GFX90A: bb.0 (%ir-block.0):
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4456458 /* regdef:AReg_128_Align2 */, def %4
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; GFX90A: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4784138 /* regdef:AReg_128_Align2 */, def %4
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; GFX90A: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %4
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4456457 /* reguse:AReg_128_Align2 */, [[COPY]]
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; GFX90A: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:AReg_128_Align2 */, [[COPY]]
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; GFX90A: S_ENDPGM 0
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%val = call i128 asm sideeffect "; def $0", "=a"()
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call void asm sideeffect "; use $0", "a"(i128 %val)
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