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AMDGPU/GlobalISel: Handle call return values
The only case that I know doesn't work is the implicit sret case when the return type doesn't fit in the return registers.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
067f635646
commit
9f712b1dc5
@ -1155,12 +1155,6 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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});
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}
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SmallVector<ArgInfo, 8> InArgs;
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if (!Info.OrigRet.Ty->isVoidTy()) {
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LLVM_DEBUG(dbgs() << "Call return values not yet handled\n");
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return false;
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}
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// If we can lower as a tail call, do that instead.
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bool CanTailCallOpt = false;
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@ -1232,9 +1226,6 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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// Now we can add the actual call instruction to the correct position.
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MIRBuilder.insertInstr(MIB);
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// If Callee is a reg, since it is used by a target specific
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// instruction, it must have a register class matching the
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// constraint of that instruction.
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@ -1248,6 +1239,31 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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1));
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}
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auto OrigInsertPt = MIRBuilder.getInsertPt();
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// Now we can add the actual call instruction to the correct position.
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MIRBuilder.insertInstr(MIB);
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// Insert this now to give us an anchor point for managing the insert point.
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MachineInstrBuilder CallSeqEnd =
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MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN);
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SmallVector<ArgInfo, 8> InArgs;
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if (!Info.OrigRet.Ty->isVoidTy()) {
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splitToValueTypes(
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MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv, false,
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[&](ArrayRef<Register> Regs, Register DstReg,
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LLT LLTy, LLT PartLLT, int VTSplitIdx) {
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assert(DstReg == Info.OrigRet.Regs[VTSplitIdx]);
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packSplitRegsToOrigType(MIRBuilder, Info.OrigRet.Regs[VTSplitIdx],
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Regs, LLTy, PartLLT);
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});
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}
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// Make sure the raw argument copies are inserted before the marshalling to
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// the original types.
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd);
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// Finally we can copy the returned value back into its virtual-register. In
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// symmetry with the arguments, the physical register must be an
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// implicit-define of the call instruction.
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@ -1260,9 +1276,10 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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}
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uint64_t CalleePopBytes = NumBytes;
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MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
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.addImm(0)
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.addImm(CalleePopBytes);
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CallSeqEnd.addImm(0)
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.addImm(CalleePopBytes);
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// Restore the insert point to after the call sequence.
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MIRBuilder.setInsertPt(MIRBuilder.getMBB(), OrigInsertPt);
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return true;
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}
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2509
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
Normal file
2509
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
Normal file
File diff suppressed because it is too large
Load Diff
85
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
Normal file
85
test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
Normal file
@ -0,0 +1,85 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
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define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
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; GCN-LABEL: name: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32
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; GCN: bb.1 (%ir-block.1):
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; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
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; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
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; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
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; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
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; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
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; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
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; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
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; GCN: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
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; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
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; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
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; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.in.val
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; GCN: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.1.out.val
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; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
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; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; GCN: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32)
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; GCN: G_STORE [[C]](s8), [[FRAME_INDEX]](p5) :: (store 1 into %ir.in.gep01, addrspace 5)
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; GCN: G_STORE [[C1]](s32), [[PTR_ADD]](p5) :: (store 4 into %ir.in.gep1, addrspace 5)
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; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
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; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32
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; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
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; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
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; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
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; GCN: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C3]](s64)
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; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
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; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
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; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
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; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
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; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
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; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; GCN: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
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; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
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; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
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; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; GCN: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
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; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C5]](s32)
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; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; GCN: $vgpr0 = COPY [[FRAME_INDEX1]](p5)
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; GCN: $vgpr1 = COPY [[FRAME_INDEX]](p5)
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; GCN: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
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; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
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; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
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; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
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; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
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; GCN: $sgpr12 = COPY [[COPY15]](s32)
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; GCN: $sgpr13 = COPY [[COPY16]](s32)
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; GCN: $sgpr14 = COPY [[COPY17]](s32)
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; GCN: $vgpr31 = COPY [[OR1]](s32)
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; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
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; GCN: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
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; GCN: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX1]], [[C2]](s32)
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; GCN: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (dereferenceable load 1 from %ir.out.gep02, addrspace 5)
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; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (dereferenceable load 4 from %ir.out.gep1, addrspace 5)
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; GCN: G_STORE [[LOAD]](s8), [[DEF]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)
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; GCN: G_STORE [[LOAD1]](s32), [[COPY10]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
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; GCN: S_ENDPGM 0
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%in.val = alloca { i8, i32 }, align 4, addrspace(5)
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%out.val = alloca { i8, i32 }, align 4, addrspace(5)
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%in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
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%in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
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store i8 3, i8 addrspace(5)* %in.gep0
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store i32 8, i32 addrspace(5)* %in.gep1
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call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val)
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%out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0
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%out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1
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%out.val0 = load i8, i8 addrspace(5)* %out.gep0
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%out.val1 = load i32, i32 addrspace(5)* %out.gep1
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store volatile i8 %out.val0, i8 addrspace(1)* undef
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store volatile i32 %out.val1, i32 addrspace(1)* undef
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ret void
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}
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