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Make the TargetMachine in MipsSubtarget a reference rather

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than a pointer to make unifying code a bit easier.

llvm-svn: 225459
This commit is contained in:
Eric Christopher 2015-01-08 18:18:57 +00:00
parent 7ba53595a5
commit 9f78ce2d4f
3 changed files with 15 additions and 15 deletions
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16
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -108,7 +108,7 @@ static std::string computeDataLayout(const MipsSubtarget &ST) {
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little, const std::string &FS, bool little,
const MipsTargetMachine *_TM) const MipsTargetMachine &TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false), ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
@ -117,11 +117,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
HasMSA(false), TM(_TM), TargetTriple(TT), HasMSA(false), TM(TM), TargetTriple(TT),
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)), TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)),
FrameLowering(MipsFrameLowering::create(*this)), FrameLowering(MipsFrameLowering::create(*this)),
TLInfo(MipsTargetLowering::create(*TM, *this)) { TLInfo(MipsTargetLowering::create(TM, *this)) {
PreviousInMips16Mode = InMips16Mode; PreviousInMips16Mode = InMips16Mode;
@ -167,7 +167,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
report_fatal_error(ISA + " is not compatible with the DSP ASE", false); report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
} }
if (NoABICalls && TM->getRelocationModel() == Reloc::PIC_) if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
report_fatal_error("position-independent code requires '-mabicalls'"); report_fatal_error("position-independent code requires '-mabicalls'");
// Set UseSmallSection. // Set UseSmallSection.
@ -194,7 +194,7 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
MipsSubtarget & MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine *TM) { const TargetMachine &TM) {
std::string CPUName = selectMipsCPU(TargetTriple, CPU); std::string CPUName = selectMipsCPU(TargetTriple, CPU);
// Parse features string. // Parse features string.
@ -202,14 +202,14 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName); InstrItins = getInstrItineraryForCPU(CPUName);
if (InMips16Mode && !TM->Options.UseSoftFloat) if (InMips16Mode && !TM.Options.UseSoftFloat)
InMips16HardFloat = true; InMips16HardFloat = true;
return *this; return *this;
} }
bool MipsSubtarget::abiUsesSoftFloat() const { bool MipsSubtarget::abiUsesSoftFloat() const {
return TM->Options.UseSoftFloat && !InMips16HardFloat; return TM.Options.UseSoftFloat && !InMips16HardFloat;
} }
bool MipsSubtarget::useConstantIslands() { bool MipsSubtarget::useConstantIslands() {
@ -218,5 +218,5 @@ bool MipsSubtarget::useConstantIslands() {
} }
Reloc::Model MipsSubtarget::getRelocationModel() const { Reloc::Model MipsSubtarget::getRelocationModel() const {
return TM->getRelocationModel(); return TM.getRelocationModel();
} }

6
lib/Target/Mips/MipsSubtarget.h
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@ -136,7 +136,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// as from the command line // as from the command line
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
const MipsTargetMachine *TM; const MipsTargetMachine &TM;
Triple TargetTriple; Triple TargetTriple;
@ -164,7 +164,7 @@ public:
/// of the specified triple. /// of the specified triple.
MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool little, const std::string &FS, bool little,
const MipsTargetMachine *TM); const MipsTargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
@ -254,7 +254,7 @@ public:
Reloc::Model getRelocationModel() const; Reloc::Model getRelocationModel() const;
MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine *TM); const TargetMachine &TM);
/// Does the system support unaligned memory access. /// Does the system support unaligned memory access.
/// ///

8
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -60,11 +60,11 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
isLittle(isLittle), isLittle(isLittle),
TLOF(make_unique<MipsTargetObjectFile>()), TLOF(make_unique<MipsTargetObjectFile>()),
Subtarget(nullptr), Subtarget(nullptr),
DefaultSubtarget(TT, CPU, FS, isLittle, this), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, this), isLittle, *this),
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
isLittle, this) { isLittle, *this) {
Subtarget = &DefaultSubtarget; Subtarget = &DefaultSubtarget;
initAsmInfo(); initAsmInfo();
} }
@ -133,7 +133,7 @@ MipsTargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this); I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this);
} }
return I.get(); return I.get();
} }