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[X86] Replace getScalarType with getVectorElementType when the type is already known to be a vector. This should result in slightly less code. NFC
llvm-svn: 251751
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52f24bb108
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@ -2179,7 +2179,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
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else if (VA.getLocInfo() == CCValAssign::AExt) {
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if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
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if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
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ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
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else
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ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
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@ -3120,7 +3120,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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break;
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case CCValAssign::AExt:
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if (Arg.getValueType().isVector() &&
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Arg.getValueType().getScalarType() == MVT::i1)
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Arg.getValueType().getVectorElementType() == MVT::i1)
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
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else if (RegVT.is128BitVector()) {
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// Special case: passing MMX values in XMM registers.
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@ -4287,7 +4287,7 @@ static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
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MVT ConstVecVT = VT;
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unsigned NumElts = VT.getVectorNumElements();
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bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
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if (!In64BitMode && VT.getScalarType() == MVT::i64) {
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if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
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ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
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Split = true;
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}
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@ -4341,7 +4341,7 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
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SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
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Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
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} else if (VT.getScalarType() == MVT::i1) {
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} else if (VT.getVectorElementType() == MVT::i1) {
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assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
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&& "Unexpected vector type");
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@ -4456,7 +4456,7 @@ static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
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Vec, ZeroIndex);
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// The blend instruction, and therefore its mask, depend on the data type.
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MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
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MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
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if (ScalarType.isFloatingPoint()) {
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// Choose either vblendps (float) or vblendpd (double).
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unsigned ScalarSize = ScalarType.getSizeInBits();
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@ -6128,7 +6128,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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unsigned NumElems = Op.getNumOperands();
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// Generate vectors for predicate vectors.
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if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
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if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
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return LowerBUILD_VECTORvXi1(Op, DAG);
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// Vectors containing all zeros can be matched by pxor and xorps later
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@ -6476,8 +6476,8 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
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return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
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if (Op.getNumOperands() == 4) {
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MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
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ResVT.getVectorNumElements()/2);
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MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
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ResVT.getVectorNumElements()/2);
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SDValue V3 = Op.getOperand(2);
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SDValue V4 = Op.getOperand(3);
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return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
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@ -6497,7 +6497,7 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
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"Unexpected number of operands in CONCAT_VECTORS");
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if (NumOfOperands > 2) {
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MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
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MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
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ResVT.getVectorNumElements()/2);
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SmallVector<SDValue, 2> Ops;
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for (unsigned i = 0; i < NumOfOperands/2; i++)
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@ -6790,7 +6790,7 @@ static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
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static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG) {
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MVT EltVT = VT.getScalarType();
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MVT EltVT = VT.getVectorElementType();
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int NumEltBits = EltVT.getSizeInBits();
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MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
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SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
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@ -6834,7 +6834,7 @@ static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
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SDValue V2, ArrayRef<int> Mask,
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SelectionDAG &DAG) {
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assert(VT.isInteger() && "Only supports integer vector types!");
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MVT EltVT = VT.getScalarType();
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MVT EltVT = VT.getVectorElementType();
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int NumEltBits = EltVT.getSizeInBits();
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SDValue Zero = DAG.getConstant(0, DL, EltVT);
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SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
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@ -8660,7 +8660,7 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
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SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
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const X86Subtarget *Subtarget, SelectionDAG &DAG) {
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assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
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assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
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MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
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assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
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@ -9734,7 +9734,7 @@ static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
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int NumElements = VT.getVectorNumElements();
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int SplitNumElements = NumElements / 2;
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MVT ScalarVT = VT.getScalarType();
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MVT ScalarVT = VT.getVectorElementType();
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MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
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// Rather than splitting build-vectors, just build two narrower build
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@ -9746,7 +9746,7 @@ static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
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MVT OrigVT = V.getSimpleValueType();
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int OrigNumElements = OrigVT.getVectorNumElements();
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int OrigSplitNumElements = OrigNumElements / 2;
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MVT OrigScalarVT = OrigVT.getScalarType();
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MVT OrigScalarVT = OrigVT.getVectorElementType();
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MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
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SDValue LoV, HiV;
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@ -11010,7 +11010,7 @@ static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
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MVT VT = Op.getSimpleValueType();
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int NumElements = VT.getVectorNumElements();
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SDLoc dl(Op);
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bool Is1BitVector = (VT.getScalarType() == MVT::i1);
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bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
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assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
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"Can't lower MMX shuffles");
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@ -12957,7 +12957,7 @@ static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
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MVT InVT = In.getSimpleValueType();
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SDLoc dl(Op);
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if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
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if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
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return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
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// Optimize vectors in AVX mode:
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@ -14100,7 +14100,7 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
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SDLoc dl(Op);
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assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
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Op.getValueType().getScalarType() == MVT::i1 &&
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Op.getValueType().getVectorElementType() == MVT::i1 &&
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"Cannot set masked compare for this operation");
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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@ -14639,7 +14639,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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if (VT.isVector() && VT.getScalarType() == MVT::i1) {
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if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
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SDValue Op1Scalar;
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if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
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Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
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@ -14915,8 +14915,8 @@ static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
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MVT InVT = In.getSimpleValueType();
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assert(VT.getSizeInBits() == InVT.getSizeInBits());
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MVT InSVT = InVT.getScalarType();
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assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
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MVT InSVT = InVT.getVectorElementType();
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assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
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return SDValue();
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@ -14935,7 +14935,7 @@ static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
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// As SRAI is only available on i16/i32 types, we expand only up to i32
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// and handle i64 separately.
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while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
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while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
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Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
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MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
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CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
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@ -14945,7 +14945,7 @@ static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
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SDValue SignExt = Curr;
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if (CurrVT != InVT) {
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unsigned SignExtShift =
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CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
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CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
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SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
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DAG.getConstant(SignExtShift, dl, MVT::i8));
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}
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@ -15005,7 +15005,7 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
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SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
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MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
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MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
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VT.getVectorNumElements()/2);
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OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
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@ -18371,7 +18371,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
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(Subtarget->hasInt256() && VT == MVT::v16i16)) &&
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ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
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SmallVector<SDValue, 8> Elts;
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EVT SVT = VT.getScalarType();
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MVT SVT = VT.getVectorElementType();
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unsigned SVTBits = SVT.getSizeInBits();
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APInt One(SVTBits, 1);
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unsigned NumElems = VT.getVectorNumElements();
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@ -22613,8 +22613,8 @@ combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
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case X86ISD::UNPCKH:
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// For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
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// shuffle into a preceding word shuffle.
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if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
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V.getSimpleValueType().getScalarType() != MVT::i16)
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if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
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V.getSimpleValueType().getVectorElementType() != MVT::i16)
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return SDValue();
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// Search for a half-shuffle which we can combine with.
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@ -22789,7 +22789,7 @@ static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
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break;
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case X86ISD::PSHUFLW:
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case X86ISD::PSHUFHW:
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assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
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assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
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if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
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return SDValue(); // We combined away this shuffle, so we're done.
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@ -23818,7 +23818,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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// FIXME: We don't support i16-element blends currently. We could and
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// should support them by making *all* the bits in the condition be set
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// rather than just the high bit and using an i8-element blend.
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if (VT.getScalarType() == MVT::i16)
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if (VT.getVectorElementType() == MVT::i16)
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return SDValue();
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// Dynamic blending was only available from SSE4.1 onward.
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if (VT.is128BitVector() && !Subtarget->hasSSE41())
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@ -24624,7 +24624,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
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// Set N0 and N1 to hold the inputs to the new wide operation.
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N0 = N0->getOperand(0);
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if (RHSConstSplat) {
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N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
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N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
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SDValue(RHSConstSplat, 0));
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SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
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N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
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