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Fix andrews changes to fit in 80 columns

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llvm-svn: 22064
This commit is contained in:
Chris Lattner 2005-05-15 19:54:37 +00:00
parent 093814c670
commit 9fc81f1162
2 changed files with 30 additions and 15 deletions
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27
lib/Target/PowerPC/PPC32ISelPattern.cpp
View File

@ -182,7 +182,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
} else {
int FI = MFI->CreateFixedObject(4, ArgOffset+4);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
DAG.getSrcValue(NULL));
}
// Build the outgoing arg thingy
argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
@ -217,7 +218,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
DAG.getConstant(SubregOffset, MVT::i32));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
DAG.getSrcValue(NULL));
}
// Every 4 bytes of argument space consumes one of the GPRs available for
@ -362,7 +364,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
--GPR_remaining;
} else {
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL)));
}
ArgOffset += 4;
break;
@ -388,7 +391,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
}
} else {
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL)));
}
ArgOffset += 8;
break;
@ -399,11 +403,13 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
--FPR_remaining;
if (isVarArg) {
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL));
MemOps.push_back(Store);
// Float varargs are always shadowed in available integer registers
if (GPR_remaining > 0) {
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
DAG.getSrcValue(NULL));
MemOps.push_back(Load);
args_to_use.push_back(Load);
--GPR_remaining;
@ -411,7 +417,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL));
SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
DAG.getSrcValue(NULL));
MemOps.push_back(Load);
args_to_use.push_back(Load);
--GPR_remaining;
@ -431,7 +438,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
}
} else {
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL)));
}
ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
break;
@ -467,7 +475,8 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
MVT::ValueType ArgVT = getValueType(ArgTy);
SDOperand Result;
if (!isVANext) {
Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList,
DAG.getSrcValue(NULL));
} else {
unsigned Amt;
if (ArgVT == MVT::i32 || ArgVT == MVT::f32)

18
lib/Target/PowerPC/PPC64ISelPattern.cpp
View File

@ -195,7 +195,8 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN,
DAG.getConstant(SubregOffset, MVT::i64));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
DAG.getSrcValue(NULL));
}
// Every 4 bytes of argument space consumes one of the GPRs available for
@ -305,7 +306,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
--GPR_remaining;
} else {
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL)));
}
ArgOffset += 8;
break;
@ -316,11 +318,13 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
--FPR_remaining;
if (isVarArg) {
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL));
MemOps.push_back(Store);
// Float varargs are always shadowed in available integer registers
if (GPR_remaining > 0) {
SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, DAG.getSrcValue(NULL));
SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff,
DAG.getSrcValue(NULL));
MemOps.push_back(Load);
args_to_use.push_back(Load);
--GPR_remaining;
@ -335,7 +339,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain,
}
} else {
MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff, DAG.getSrcValue(NULL)));
Args[i].first, PtrOff,
DAG.getSrcValue(NULL)));
}
ArgOffset += 8;
break;
@ -371,7 +376,8 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
MVT::ValueType ArgVT = getValueType(ArgTy);
SDOperand Result;
if (!isVANext) {
Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL));
Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList,
DAG.getSrcValue(NULL));
} else {
Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
DAG.getConstant(8, VAList.getValueType()));