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Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. llvm-svn: 156075
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@ -421,7 +421,9 @@ public:
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/// TableGen will synthesize missing A sub-classes.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const =0;
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const TargetRegisterClass *B, unsigned Idx) const {
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llvm_unreachable("Target has no sub-registers");
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}
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/// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
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/// supports the sub-register index Idx.
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@ -436,7 +438,10 @@ public:
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///
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/// TableGen will synthesize missing RC sub-classes.
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virtual const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
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getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
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assert(Idx == 0 && "Target has no sub-registers");
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return RC;
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}
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/// composeSubRegIndices - Return the subregister index you get from composing
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/// two subregister indices.
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@ -672,14 +672,16 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
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<< " explicit " << ClassName
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<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
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<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
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<< " { return false; }\n"
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<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
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<< " const TargetRegisterClass *"
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"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
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<< " const TargetRegisterClass *getMatchingSuperRegClass("
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"const TargetRegisterClass*, const TargetRegisterClass*, "
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"unsigned) const;\n"
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<< " const RegClassWeight &getRegClassWeight("
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<< " { return false; }\n";
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if (!RegBank.getSubRegIndices().empty()) {
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OS << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
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<< " const TargetRegisterClass *"
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"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
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<< " const TargetRegisterClass *getMatchingSuperRegClass("
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"const TargetRegisterClass*, const TargetRegisterClass*, "
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"unsigned) const;\n";
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}
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OS << " const RegClassWeight &getRegClassWeight("
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<< "const TargetRegisterClass *RC) const;\n"
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<< " unsigned getNumRegPressureSets() const;\n"
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<< " const char *getRegPressureSetName(unsigned Idx) const;\n"
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@ -945,37 +947,36 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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// Emit composeSubRegIndices
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OS << "unsigned " << ClassName
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<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
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<< " switch (IdxA) {\n"
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<< " default:\n return IdxB;\n";
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for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
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bool Open = false;
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for (unsigned j = 0; j != e; ++j) {
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if (CodeGenSubRegIndex *Comp =
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if (!SubRegIndices.empty()) {
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OS << "unsigned " << ClassName
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<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
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<< " switch (IdxA) {\n"
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<< " default:\n return IdxB;\n";
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for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
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bool Open = false;
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for (unsigned j = 0; j != e; ++j) {
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if (CodeGenSubRegIndex *Comp =
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SubRegIndices[i]->compose(SubRegIndices[j])) {
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if (!Open) {
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OS << " case " << SubRegIndices[i]->getQualifiedName()
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<< ": switch(IdxB) {\n default: return IdxB;\n";
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Open = true;
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if (!Open) {
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OS << " case " << SubRegIndices[i]->getQualifiedName()
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<< ": switch(IdxB) {\n default: return IdxB;\n";
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Open = true;
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}
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OS << " case " << SubRegIndices[j]->getQualifiedName()
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<< ": return " << Comp->getQualifiedName() << ";\n";
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}
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OS << " case " << SubRegIndices[j]->getQualifiedName()
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<< ": return " << Comp->getQualifiedName() << ";\n";
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}
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if (Open)
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OS << " }\n";
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}
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if (Open)
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OS << " }\n";
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OS << " }\n}\n\n";
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}
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OS << " }\n}\n\n";
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// Emit getSubClassWithSubReg.
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OS << "const TargetRegisterClass *" << ClassName
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<< "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
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" const {\n";
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if (SubRegIndices.empty()) {
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OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
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<< " return RC;\n";
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} else {
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if (!SubRegIndices.empty()) {
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OS << "const TargetRegisterClass *" << ClassName
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<< "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
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<< " const {\n";
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// Use the smallest type that can hold a regclass ID with room for a
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// sentinel.
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if (RegisterClasses.size() < UINT8_MAX)
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@ -1002,17 +1003,14 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< " if (!Idx) return RC;\n --Idx;\n"
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<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
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<< " unsigned TV = Table[RC->getID()][Idx];\n"
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<< " return TV ? getRegClass(TV - 1) : 0;\n";
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<< " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
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}
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OS << "}\n\n";
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// Emit getMatchingSuperRegClass.
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OS << "const TargetRegisterClass *" << ClassName
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<< "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
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" const TargetRegisterClass *B, unsigned Idx) const {\n";
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if (SubRegIndices.empty()) {
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OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
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} else {
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if (!SubRegIndices.empty()) {
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OS << "const TargetRegisterClass *" << ClassName
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<< "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
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<< " const TargetRegisterClass *B, unsigned Idx) const {\n";
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// We need to find the largest sub-class of A such that every register has
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// an Idx sub-register in B. Map (B, Idx) to a bit-vector of
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// super-register classes that map into B. Then compute the largest common
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@ -1047,9 +1045,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
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<< " if (unsigned Common = TV[i] & SC[i])\n"
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<< " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
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<< " return 0;\n";
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<< " return 0;\n}\n\n";
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}
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OS << "}\n\n";
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EmitRegUnitPressure(OS, RegBank, ClassName);
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