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[AArch64] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the AArch64 dot-product instructions introduced in v8.2-A. Differential revisioon: https://reviews.llvm.org/D46107 llvm-svn: 331036
This commit is contained in:
Oliver Stannard
parent
c0666ae6d5
commit
9fd29cce52
@ -149,6 +149,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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class AdvSIMD_1Arg_Intrinsic
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: Intrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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class AdvSIMD_Dot_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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}
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// Arithmetic ops
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@ -415,6 +420,10 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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// Scalar FP Inexact Narrowing
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def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
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[IntrNoMem]>;
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// v8.2-A Dot Product
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def int_aarch64_neon_udot : AdvSIMD_Dot_Intrinsic;
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def int_aarch64_neon_sdot : AdvSIMD_Dot_Intrinsic;
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}
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let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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@ -4595,11 +4595,24 @@ class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<3> size, bits<5> opcode,
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}
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class BaseSIMDThreeSameVectorDot<bit Q, bit U, string asm, string kind1,
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string kind2> :
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BaseSIMDThreeSameVector<Q, U, 0b100, 0b10010, V128, asm, kind1, [] > {
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string kind2, RegisterOperand RegType,
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ValueType AccumType, ValueType InputType,
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SDPatternOperator OpNode> :
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BaseSIMDThreeSameVectorTied<Q, U, 0b100, 0b10010, RegType, asm, kind1,
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[(set (AccumType RegType:$dst),
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(OpNode (AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType RegType:$Rm)))]> {
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let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
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}
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multiclass SIMDThreeSameVectorDot<bit U, string asm, SDPatternOperator OpNode> {
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def v8i8 : BaseSIMDThreeSameVectorDot<0, U, asm, ".2s", ".8b", V64,
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v2i32, v8i8, OpNode>;
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def v16i8 : BaseSIMDThreeSameVectorDot<1, U, asm, ".4s", ".16b", V128,
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v4i32, v16i8, OpNode>;
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}
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// All operand sizes distinguished in the encoding.
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multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
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SDPatternOperator OpNode> {
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@ -7029,14 +7042,31 @@ class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
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// ARMv8.2 Index Dot product instructions
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class BaseSIMDThreeSameVectorDotIndex<bit Q, bit U, string asm, string dst_kind,
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string lhs_kind, string rhs_kind> :
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BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, V128, V128, V128, VectorIndexS,
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asm, "", dst_kind, lhs_kind, rhs_kind, []> {
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string lhs_kind, string rhs_kind,
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RegisterOperand RegType,
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ValueType AccumType, ValueType InputType,
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SDPatternOperator OpNode> :
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BaseSIMDIndexedTied<Q, U, 0b0, 0b10, 0b1110, RegType, RegType, V128,
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VectorIndexS, asm, "", dst_kind, lhs_kind, rhs_kind,
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[(set (AccumType RegType:$dst),
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(AccumType (OpNode (AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType (bitconvert (AccumType
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(AArch64duplane32 (v4i32 V128:$Rm),
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VectorIndexS:$idx)))))))]> {
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bits<2> idx;
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let Inst{21} = idx{0}; // L
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let Inst{11} = idx{1}; // H
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}
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multiclass SIMDThreeSameVectorDotIndex<bit U, string asm,
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SDPatternOperator OpNode> {
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def v8i8 : BaseSIMDThreeSameVectorDotIndex<0, U, asm, ".2s", ".8b", ".4b", V64,
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v2i32, v8i8, OpNode>;
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def v16i8 : BaseSIMDThreeSameVectorDotIndex<1, U, asm, ".4s", ".16b", ".4b", V128,
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v4i32, v16i8, OpNode>;
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}
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multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
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SDPatternOperator OpNode> {
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let Predicates = [HasNEON, HasFullFP16] in {
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@ -453,14 +453,10 @@ def ISB : CRmSystemI<barrier_op, 0b110, "isb",
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// ARMv8.2 Dot Product
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let Predicates = [HasDotProd] in {
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def UDOT2S : BaseSIMDThreeSameVectorDot<0, 1, "udot", ".2s", ".8b">;
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def SDOT2S : BaseSIMDThreeSameVectorDot<0, 0, "sdot", ".2s", ".8b">;
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def UDOT4S : BaseSIMDThreeSameVectorDot<1, 1, "udot", ".4s", ".16b">;
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def SDOT4S : BaseSIMDThreeSameVectorDot<1, 0, "sdot", ".4s", ".16b">;
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def UDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 1, "udot", ".2s", ".8b", ".4b">;
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def SDOTIDX2S : BaseSIMDThreeSameVectorDotIndex<0, 0, "sdot", ".2s", ".8b", ".4b">;
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def UDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 1, "udot", ".4s", ".16b", ".4b">;
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def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;
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defm SDOT : SIMDThreeSameVectorDot<0, "sdot", int_aarch64_neon_sdot>;
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defm UDOT : SIMDThreeSameVectorDot<1, "udot", int_aarch64_neon_udot>;
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defm SDOTlane : SIMDThreeSameVectorDotIndex<0, "sdot", int_aarch64_neon_sdot>;
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defm UDOTlane : SIMDThreeSameVectorDotIndex<1, "udot", int_aarch64_neon_udot>;
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}
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let Predicates = [HasRCPC] in {
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126
test/CodeGen/AArch64/neon-dot-product.ll
Normal file
126
test/CodeGen/AArch64/neon-dot-product.ll
Normal file
@ -0,0 +1,126 @@
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; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
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declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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declare <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_u32:
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; CHECK: udot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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