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[InstSimplify] move/add/regenerate checks for tests; NFC

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llvm-svn: 330515
This commit is contained in:
Sanjay Patel 2018-04-21 16:23:47 +00:00
parent 66bfc0f0fd
commit a01fc5df78
6 changed files with 90 additions and 27 deletions
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9
test/Transforms/InstCombine/div.ll
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@ -21,15 +21,6 @@ define i32 @test2(i32 %A) {
ret i32 %B
}
define i32 @test3(i32 %A) {
; => 0, don't need to keep traps
; CHECK-LABEL: @test3(
; CHECK-NEXT: ret i32 0
;
%B = sdiv i32 0, %A ; <i32> [#uses=1]
ret i32 %B
}
define i32 @test4(i32 %A) {
; 0-A
; CHECK-LABEL: @test4(

8
test/Transforms/InstCombine/rem.ll
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@ -150,14 +150,6 @@ define i32 @test1(i32 %A) {
ret i32 %B
}
define i32 @test2(i32 %A) { ; 0 % X = 0, we don't need to preserve traps
; CHECK-LABEL: @test2(
; CHECK-NEXT: ret i32 0
;
%B = srem i32 0, %A
ret i32 %B
}
define i32 @test3(i32 %A) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: [[B:%.*]] = and i32 %A, 7

42
test/Transforms/InstSimplify/div.ll
View File

@ -1,5 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instsimplify -S | FileCheck %s
define i32 @zero_dividend(i32 %A) {
; CHECK-LABEL: @zero_dividend(
; CHECK-NEXT: ret i32 0
;
%B = sdiv i32 0, %A
ret i32 %B
}
define <2 x i32> @zero_dividend_vector(<2 x i32> %A) {
; CHECK-LABEL: @zero_dividend_vector(
; CHECK-NEXT: ret <2 x i32> zeroinitializer
;
%B = udiv <2 x i32> zeroinitializer, %A
ret <2 x i32> %B
}
define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) {
; CHECK-LABEL: @zero_dividend_vector_undef_elt(
; CHECK-NEXT: [[B:%.*]] = sdiv <2 x i32> <i32 0, i32 undef>, [[A:%.*]]
; CHECK-NEXT: ret <2 x i32> [[B]]
;
%B = sdiv <2 x i32> <i32 0, i32 undef>, %A
ret <2 x i32> %B
}
; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) {
@ -56,7 +82,7 @@ define <2 x i8> @udiv_undef_elt_vec(<2 x i8> %x) {
define <2 x i1> @sdiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
; CHECK-LABEL: @sdiv_bool_vec(
; CHECK-NEXT: ret <2 x i1> %x
; CHECK-NEXT: ret <2 x i1> [[X:%.*]]
;
%div = sdiv <2 x i1> %x, %y
ret <2 x i1> %div
@ -64,7 +90,7 @@ define <2 x i1> @sdiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
define <2 x i1> @udiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
; CHECK-LABEL: @udiv_bool_vec(
; CHECK-NEXT: ret <2 x i1> %x
; CHECK-NEXT: ret <2 x i1> [[X:%.*]]
;
%div = udiv <2 x i1> %x, %y
ret <2 x i1> %div
@ -81,7 +107,7 @@ define i32 @udiv_dividend_known_smaller_than_constant_divisor(i32 %x) {
define i32 @not_udiv_dividend_known_smaller_than_constant_divisor(i32 %x) {
; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_constant_divisor(
; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 251
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], 251
; CHECK-NEXT: ret i32 [[DIV]]
;
@ -101,7 +127,7 @@ define i32 @udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
define i32 @not_udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
; CHECK-LABEL: @not_udiv_constant_dividend_known_smaller_than_divisor(
; CHECK-NEXT: [[OR:%.*]] = or i32 %x, 251
; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 251, [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
@ -114,8 +140,8 @@ define i32 @not_udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
define i32 @udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
; CHECK-LABEL: @udiv_dividend_known_smaller_than_divisor(
; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 250
; CHECK-NEXT: [[OR:%.*]] = or i32 %y, 251
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 250
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;
@ -127,8 +153,8 @@ define i32 @udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
define i32 @not_udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_divisor(
; CHECK-NEXT: [[AND:%.*]] = and i32 %x, 251
; CHECK-NEXT: [[OR:%.*]] = or i32 %y, 251
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 251
; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 251
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
; CHECK-NEXT: ret i32 [[DIV]]
;

9
test/Transforms/InstSimplify/mul.ll
View File

@ -34,3 +34,12 @@ define <16 x i8> @mul_by_0_vec(<16 x i8> %a) {
ret <16 x i8> %b
}
define <2 x i8> @mul_by_0_vec_undef_elt(<2 x i8> %a) {
; CHECK-LABEL: @mul_by_0_vec_undef_elt(
; CHECK-NEXT: [[B:%.*]] = mul <2 x i8> [[A:%.*]], <i8 undef, i8 0>
; CHECK-NEXT: ret <2 x i8> [[B]]
;
%b = mul <2 x i8> %a, <i8 undef, i8 0>
ret <2 x i8> %b
}

24
test/Transforms/InstSimplify/negate.ll
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@ -17,6 +17,15 @@ define <2 x i32> @negate_nuw_vec(<2 x i32> %x) {
ret <2 x i32> %neg
}
define <2 x i32> @negate_nuw_vec_undef_elt(<2 x i32> %x) {
; CHECK-LABEL: @negate_nuw_vec_undef_elt(
; CHECK-NEXT: [[NEG:%.*]] = sub nuw <2 x i32> <i32 0, i32 undef>, [[X:%.*]]
; CHECK-NEXT: ret <2 x i32> [[NEG]]
;
%neg = sub nuw <2 x i32> <i32 0, i32 undef>, %x
ret <2 x i32> %neg
}
define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
; CHECK-LABEL: @negate_zero_or_minsigned_nsw(
; CHECK-NEXT: ret i8 0
@ -35,9 +44,20 @@ define <2 x i8> @negate_zero_or_minsigned_nsw_vec(<2 x i8> %x) {
ret <2 x i8> %neg
}
define <2 x i8> @negate_zero_or_minsigned_nsw_vec_undef_elt(<2 x i8> %x) {
; CHECK-LABEL: @negate_zero_or_minsigned_nsw_vec_undef_elt(
; CHECK-NEXT: [[SIGNBIT:%.*]] = shl <2 x i8> [[X:%.*]], <i8 7, i8 7>
; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i8> <i8 undef, i8 0>, [[SIGNBIT]]
; CHECK-NEXT: ret <2 x i8> [[NEG]]
;
%signbit = shl <2 x i8> %x, <i8 7, i8 7>
%neg = sub nsw <2 x i8> <i8 undef, i8 0>, %signbit
ret <2 x i8> %neg
}
define i8 @negate_zero_or_minsigned(i8 %x) {
; CHECK-LABEL: @negate_zero_or_minsigned(
; CHECK-NEXT: [[SIGNBIT:%.*]] = shl i8 %x, 7
; CHECK-NEXT: [[SIGNBIT:%.*]] = shl i8 [[X:%.*]], 7
; CHECK-NEXT: ret i8 [[SIGNBIT]]
;
%signbit = shl i8 %x, 7
@ -47,7 +67,7 @@ define i8 @negate_zero_or_minsigned(i8 %x) {
define <2 x i8> @negate_zero_or_minsigned_vec(<2 x i8> %x) {
; CHECK-LABEL: @negate_zero_or_minsigned_vec(
; CHECK-NEXT: [[SIGNBIT:%.*]] = and <2 x i8> %x, <i8 -128, i8 -128>
; CHECK-NEXT: [[SIGNBIT:%.*]] = and <2 x i8> [[X:%.*]], <i8 -128, i8 -128>
; CHECK-NEXT: ret <2 x i8> [[SIGNBIT]]
;
%signbit = and <2 x i8> %x, <i8 128, i8 128>

25
test/Transforms/InstSimplify/rem.ll
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@ -1,6 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instsimplify -S | FileCheck %s
define i32 @zero_dividend(i32 %A) {
; CHECK-LABEL: @zero_dividend(
; CHECK-NEXT: ret i32 0
;
%B = urem i32 0, %A
ret i32 %B
}
define <2 x i32> @zero_dividend_vector(<2 x i32> %A) {
; CHECK-LABEL: @zero_dividend_vector(
; CHECK-NEXT: ret <2 x i32> zeroinitializer
;
%B = srem <2 x i32> zeroinitializer, %A
ret <2 x i32> %B
}
define <2 x i32> @zero_dividend_vector_undef_elt(<2 x i32> %A) {
; CHECK-LABEL: @zero_dividend_vector_undef_elt(
; CHECK-NEXT: [[B:%.*]] = urem <2 x i32> <i32 undef, i32 0>, [[A:%.*]]
; CHECK-NEXT: ret <2 x i32> [[B]]
;
%B = urem <2 x i32> <i32 undef, i32 0>, %A
ret <2 x i32> %B
}
; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
define <2 x i8> @srem_zero_elt_vec_constfold(<2 x i8> %x) {