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CellSPU:

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Revert inadvertent mis-fix of fneg.

llvm-svn: 67084
This commit is contained in:
Scott Michel 2009-03-17 16:45:16 +00:00
parent 41c5cb70e2
commit a023598ad3
3 changed files with 17 additions and 17 deletions
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4
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
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@ -865,12 +865,12 @@ SPUDAGToDAGISel::Select(SDValue Op) {
SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
SDNode *signMask = 0;
unsigned Opc = SPU::ORfneg64;
unsigned Opc = SPU::XORfneg64;
if (OpVT == MVT::f64) {
signMask = SelectI64Constant(negConst, MVT::i64, dl);
} else if (OpVT == MVT::v2f64) {
Opc = SPU::ORfnegvec;
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
MVT::v2i64,
negConst, negConst));

28
lib/Target/CellSPU/SPUInstrInfo.td
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@ -1483,17 +1483,6 @@ multiclass BitwiseOr
def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
[/* no pattern */]>;
// OR instructions used to negate f32 and f64 quantities.
def fneg32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
[/* no pattern */]>;
def fneg64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
[/* no pattern */]>;
def fnegvec: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
[/* no pattern, see fneg{32,64} */]>;
// scalar->vector promotion, prefslot2vec:
def v16i8_i8: ORPromoteScalar<R8C>;
def v8i16_i16: ORPromoteScalar<R16C>;
@ -1797,6 +1786,17 @@ multiclass BitwiseExclusiveOr
def r32: XORRegInst<R32C>;
def r16: XORRegInst<R16C>;
def r8: XORRegInst<R8C>;
// XOR instructions used to negate f32 and f64 quantities.
def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
[/* no pattern */]>;
def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
[/* no pattern */]>;
def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
[/* no pattern, see fneg{32,64} */]>;
}
defm XOR : BitwiseExclusiveOr;
@ -4298,11 +4298,11 @@ def FNMAv2f64 :
//===----------------------------------------------------------------------==//
def : Pat<(fneg (v4f32 VECREG:$rA)),
(ORfnegvec (v4f32 VECREG:$rA),
(v4f32 (ILHUv4i32 0x8000)))>;
(XORfnegvec (v4f32 VECREG:$rA),
(v4f32 (ILHUv4i32 0x8000)))>;
def : Pat<(fneg R32FP:$rA),
(ORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
(XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
// Floating point absolute value
// Note: f64 fabs is custom-selected.

2
test/CodeGen/CellSPU/fneg-fabs.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep 32768 %t1.s | count 2
; RUN: grep or %t1.s | count 4
; RUN: grep xor %t1.s | count 4
; RUN: grep and %t1.s | count 2
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"