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[SelectionDAG] Teach the vector scalarizer about FP conversions.

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This adds support for legalization of instructions of the form:

  [fp_conv] <1 x i1> %op to <1 x double>

where fp_conv is one of fpto[us]i, [us]itofp.  This used to assert
because they were simply missing from the vector operand scalarizer.

A similar problem arose in r190830, with trunc instead.

Fixes PR20778.

Differential Revision: http://reviews.llvm.org/D5810

llvm-svn: 220533
This commit is contained in:
Ahmed Bougacha 2014-10-23 22:49:25 +00:00
parent 4e0335a62d
commit a035d19b50
2 changed files with 48 additions and 0 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -411,6 +411,10 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
case ISD::TRUNCATE: case ISD::TRUNCATE:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
Res = ScalarizeVecOp_UnaryOp(N); Res = ScalarizeVecOp_UnaryOp(N);
break; break;
case ISD::CONCAT_VECTORS: case ISD::CONCAT_VECTORS:

44
test/CodeGen/AArch64/fpconv-vector-op-scalarize.ll Normal file
View File

@ -0,0 +1,44 @@
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
; PR20778
; Check that the legalizer doesn't crash when scalarizing FP conversion
; instructions' operands. The operands are all illegal on AArch64,
; ensuring they are legalized. The results are all legal.
define <1 x double> @test_sitofp(<1 x i1> %in) {
; CHECK-LABEL: test_sitofp:
; CHECK: sbfx w8, w0, #0, #1
; CHECK-NEXT: scvtf d0, w8
; CHECK-NEXT: ret
entry:
%0 = sitofp <1 x i1> %in to <1 x double>
ret <1 x double> %0
}
define <1 x double> @test_uitofp(<1 x i1> %in) {
; CHECK-LABEL: test_uitofp:
; CHECK: and w8, w0, #0x1
; CHECK-NEXT: ucvtf d0, w8
; CHECK-NEXT: ret
entry:
%0 = uitofp <1 x i1> %in to <1 x double>
ret <1 x double> %0
}
define <1 x i64> @test_fptosi(<1 x fp128> %in) {
; CHECK-LABEL: test_fptosi:
; CHECK: bl ___fixtfdi
; CHECK-NEXT: fmov d0, x0
entry:
%0 = fptosi <1 x fp128> %in to <1 x i64>
ret <1 x i64> %0
}
define <1 x i64> @test_fptoui(<1 x fp128> %in) {
; CHECK-LABEL: test_fptoui:
; CHECK: bl ___fixunstfdi
; CHECK-NEXT: fmov d0, x0
entry:
%0 = fptoui <1 x fp128> %in to <1 x i64>
ret <1 x i64> %0
}