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The dag isel generator generates this now

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llvm-svn: 23984
This commit is contained in:
Chris Lattner 2005-10-25 20:36:10 +00:00
parent 60d02fd01f
commit a050c43068
2 changed files with 0 additions and 64 deletions
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32
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -183,38 +183,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
return SDOperand(N, 0);
}
case ISD::TokenFactor: {
SDOperand New;
if (N->getNumOperands() == 2) {
SDOperand Op0 = Select(N->getOperand(0));
SDOperand Op1 = Select(N->getOperand(1));
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
} else {
std::vector<SDOperand> Ops;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
Ops.push_back(Select(N->getOperand(i)));
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
}
CodeGenMap[Op] = New;
return New;
}
case ISD::CopyFromReg: {
SDOperand Chain = Select(N->getOperand(0));
if (Chain == N->getOperand(0)) return Op; // No change
SDOperand New = CurDAG->getCopyFromReg(Chain,
cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
return New.getValue(Op.ResNo);
}
case ISD::CopyToReg: {
SDOperand Chain = Select(N->getOperand(0));
SDOperand Reg = N->getOperand(1);
SDOperand Val = Select(N->getOperand(2));
SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
Chain, Reg, Val);
CodeGenMap[Op] = New;
return New;
}
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i64)
CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);

32
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -844,38 +844,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
case ISD::CALL: return SelectCALL(Op);
case ISD::TAILCALL: return SelectCALL(Op);
case ISD::TokenFactor: {
SDOperand New;
if (N->getNumOperands() == 2) {
SDOperand Op0 = Select(N->getOperand(0));
SDOperand Op1 = Select(N->getOperand(1));
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
} else {
std::vector<SDOperand> Ops;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
Ops.push_back(Select(N->getOperand(i)));
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
}
CodeGenMap[Op] = New;
return New;
}
case ISD::CopyFromReg: {
SDOperand Chain = Select(N->getOperand(0));
if (Chain == N->getOperand(0)) return Op; // No change
SDOperand New = CurDAG->getCopyFromReg(Chain,
cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
return New.getValue(Op.ResNo);
}
case ISD::CopyToReg: {
SDOperand Chain = Select(N->getOperand(0));
SDOperand Reg = N->getOperand(1);
SDOperand Val = Select(N->getOperand(2));
SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
Chain, Reg, Val);
CodeGenMap[Op] = New;
return New;
}
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i32)
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);