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Target: Remove unused patterns and transforms. NFC.

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llvm-svn: 283515
This commit is contained in:
Peter Collingbourne 2016-10-07 00:30:49 +00:00
parent 7f4bcd51cf
commit a067ba4392
13 changed files with 0 additions and 203 deletions
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13
lib/Target/AMDGPU/AMDGPUInstructions.td
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@ -362,11 +362,6 @@ multiclass AtomicCmpSwapLocal <SDNode cmp_swap_node> {
defm atomic_cmp_swap : AtomicCmpSwapLocal <atomic_cmp_swap>;
def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
(AMDGPUstore_mskor node:$val, node:$ptr), [{
return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
}]>;
class global_binary_atomic_op<SDNode atomic_op> : PatFrag<
(ops node:$ptr, node:$value),
(atomic_op node:$ptr, node:$value),
@ -385,11 +380,6 @@ def atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
def atomic_cmp_swap_global : global_binary_atomic_op<AMDGPUatomic_cmp_swap>;
def atomic_cmp_swap_global_nortn : PatFrag<
(ops node:$ptr, node:$value),
(atomic_cmp_swap_global node:$ptr, node:$value),
[{ return SDValue(N, 0).use_empty(); }]
>;
//===----------------------------------------------------------------------===//
// Misc Pattern Fragments
@ -603,9 +593,6 @@ def sub_oneuse : HasOneUseBinOp<sub>;
def select_oneuse : HasOneUseTernaryOp<select>;
// 24-bit arithmetic patterns
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
// Special conversion patterns
def cvt_rpi_i32_f32 : PatFrag <

6
lib/Target/AMDGPU/BUFInstructions.td
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@ -699,12 +699,6 @@ def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",
// MUBUF Patterns
//===----------------------------------------------------------------------===//
def mubuf_vaddr_offset : PatFrag<
(ops node:$ptr, node:$offset, node:$imm_offset),
(add (add node:$ptr, node:$offset), node:$imm_offset)
>;
let Predicates = [isGCN] in {
// int_SI_vs_load_input

14
lib/Target/AMDGPU/R600Instructions.td
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@ -242,20 +242,6 @@ def TEX_SHADOW_ARRAY : PatLeaf<
}]
>;
def TEX_MSAA : PatLeaf<
(imm),
[{uint32_t TType = (uint32_t)N->getZExtValue();
return TType == 14;
}]
>;
def TEX_ARRAY_MSAA : PatLeaf<
(imm),
[{uint32_t TType = (uint32_t)N->getZExtValue();
return TType == 15;
}]
>;
class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
dag outs, dag ins, string asm, list<dag> pattern> :
InstR600ISA <outs, ins, asm, pattern>,

108
lib/Target/Hexagon/HexagonOperands.td
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@ -146,31 +146,6 @@ def s29_3ImmPred : PatLeaf<(i32 imm), [{
return isShiftedInt<29,3>(v);
}]>;
def s16ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<16>(v);
}]>;
def s11_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<11>(v);
}]>;
def s11_1ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,1>(v);
}]>;
def s11_2ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,2>(v);
}]>;
def s11_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,3>(v);
}]>;
def s10ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<10>(v);
@ -211,66 +186,21 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{
return isShiftedInt<4,3>(v);
}]>;
def u64ImmPred : PatLeaf<(i64 imm), [{
// Adding "N ||" to suppress gcc unused warning.
return (N || true);
}]>;
def u32ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<32>(v);
}]>;
def u32_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<32>(v);
}]>;
def u31_1ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<31,1>(v);
}]>;
def u30_2ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<30,2>(v);
}]>;
def u29_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<29,3>(v);
}]>;
def u26_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<26,6>(v);
}]>;
def u16_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<16>(v);
}]>;
def u16_1ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<16,1>(v);
}]>;
def u16_2ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<16,2>(v);
}]>;
def u11_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<11,3>(v);
}]>;
def u10ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<10>(v);
}]>;
def u9ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<9>(v);
@ -287,11 +217,6 @@ def u7StrictPosImmPred : ImmLeaf<i32, [{
return isUInt<7>(Imm) && Imm > 0;
}]>;
def u7ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<7>(v);
}]>;
def u6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<6>(v);
@ -312,11 +237,6 @@ def u6_2ImmPred : PatLeaf<(i32 imm), [{
return isShiftedUInt<6,2>(v);
}]>;
def u6_3ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<6,3>(v);
}]>;
def u5ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<5>(v);
@ -337,16 +257,6 @@ def u2ImmPred : PatLeaf<(i32 imm), [{
return isUInt<2>(v);
}]>;
def u1ImmPred : PatLeaf<(i1 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<1>(v);
}]>;
def u1ImmPred32 : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<1>(v);
}]>;
def m5ImmPred : PatLeaf<(i32 imm), [{
// m5ImmPred predicate - True if the number is in range -1 .. -31
// and will fit in a 5 bit field when made positive, for use in memops.
@ -460,15 +370,6 @@ def s4_7ImmPred : PatLeaf<(i32 imm), [{
return false;
}]>;
def s3_7ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 9-bit sign extended field and
// is 128-byte aligned.
return isShiftedInt<3,7>(v);
return false;
}]>;
def s4_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
@ -478,15 +379,6 @@ def s4_6ImmPred : PatLeaf<(i32 imm), [{
return false;
}]>;
def s3_6ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (HST->hasV60TOps())
// Return true if the immediate can fit in a 9-bit sign extended field and
// is 64-byte aligned.
return isShiftedInt<3,6>(v);
return false;
}]>;
// This complex pattern exists only to create a machine instruction operand
// of type "frame index". There doesn't seem to be a way to do that directly

3
lib/Target/Lanai/LanaiInstrInfo.td
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@ -115,9 +115,6 @@ def imm10 : Operand<i32>, PatLeaf<(imm), [{
let ParserMatchClass = Imm10AsmOperand;
}
def immZExt21 : PatLeaf<(imm),
[{return isUInt<21>(N->getZExtValue()); }], LO21>;
def LoImm16AsmOperand : AsmOperandClass { let Name = "LoImm16"; }
def i32lo16z : Operand<i32>, PatLeaf<(i32 imm), [{
// i32lo16 predicate - true if the 32-bit immediate has only rightmost 16

5
lib/Target/Mips/Mips64InstrInfo.td
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@ -15,11 +15,6 @@
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
return getImm(N, (unsigned)N->getZExtValue() - 32);
}]>;
// shamt must fit in 6 bits.
def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;

4
lib/Target/Mips/MipsInstrInfo.td
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@ -1081,10 +1081,6 @@ def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
// e.g. addi, andi
def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
// Node immediate fits as 15-bit sign extended on target immediate.
// e.g. addi, andi
def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
// Node immediate fits as 7-bit zero extended on target immediate.
def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;

4
lib/Target/Mips/MipsMSAInstrInfo.td
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@ -389,10 +389,6 @@ def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
(fmul node:$ws, (fexp2 node:$wt))>;
// Immediates
def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
// Instruction encoding.
class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;

15
lib/Target/NVPTX/NVPTXInstrInfo.td
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@ -71,10 +71,6 @@ def CmpLT : PatLeaf<(i32 2)>;
def CmpLE : PatLeaf<(i32 3)>;
def CmpGT : PatLeaf<(i32 4)>;
def CmpGE : PatLeaf<(i32 5)>;
def CmpLO : PatLeaf<(i32 6)>;
def CmpLS : PatLeaf<(i32 7)>;
def CmpHI : PatLeaf<(i32 8)>;
def CmpHS : PatLeaf<(i32 9)>;
def CmpEQU : PatLeaf<(i32 10)>;
def CmpNEU : PatLeaf<(i32 11)>;
def CmpLTU : PatLeaf<(i32 12)>;
@ -90,10 +86,6 @@ def CmpLT_FTZ : PatLeaf<(i32 0x102)>;
def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
@ -107,13 +99,6 @@ def CmpMode : Operand<i32> {
let PrintMethod = "printCmpMode";
}
def F32ConstZero : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstantFP(0.0, MVT::f32);
}]>;
def F32ConstOne : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstantFP(1.0, MVT::f32);
}]>;
//===----------------------------------------------------------------------===//
// NVPTX Instruction Predicate Definitions
//===----------------------------------------------------------------------===//

10
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -65,16 +65,6 @@ def SRL64 : SDNodeXForm<imm, [{
: getI32Imm(0, SDLoc(N));
}]>;
def HI32_48 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getZExtValue() >> 32, SDLoc(N)));
}]>;
def HI48_64 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
return getI32Imm((unsigned short)(N->getZExtValue() >> 48, SDLoc(N)));
}]>;
//===----------------------------------------------------------------------===//
// Calls.

9
lib/Target/SystemZ/SystemZOperators.td
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@ -387,15 +387,6 @@ def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
// Match extensions of an i32 to an i64, followed by an AND of the low
// i8 or i16 part.
def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>;
def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>;
// Typed floating-point loads.
def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
// Extending loads in which the extension type can be signed.
def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
unsigned Type = cast<LoadSDNode>(N)->getExtensionType();

4
lib/Target/X86/X86InstrFragmentsSIMD.td
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@ -29,7 +29,6 @@ def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
def load_mvmmx : PatFrag<(ops node:$ptr),
(x86mmx (MMX_X86movw2d (load node:$ptr)))>;
def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
//===----------------------------------------------------------------------===//
// SSE specific DAG Nodes.
@ -704,9 +703,6 @@ def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
|| cast<LoadSDNode>(N)->getAlignment() >= 16;
}]>;
def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
// 128-bit memop pattern fragments
// NOTE: all 128-bit integer vector loads are promoted to v2i64
def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;

8
lib/Target/XCore/XCoreInstrInfo.td
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@ -146,18 +146,10 @@ def immU6 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 6);
}]>;
def immU10 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 10);
}]>;
def immU16 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 16);
}]>;
def immU20 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 20);
}]>;
def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
def immBitp : PatLeaf<(imm), [{