RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 11:33:24 +02:00
Code Issues Projects Releases Wiki Activity

Teach getTargetVShiftNode about TargetConstant nodes.

Browse Source 
llvm-svn: 160234
This commit is contained in:
Nadav Rotem 2012-07-15 20:27:43 +00:00
parent a759fed621
commit a09775b875
2 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/X86/X86ISelLowering.cpp
View File

@ -9433,12 +9433,15 @@ static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
if (isa<ConstantSDNode>(ShAmt)) {
// Constant may be a TargetConstant. Use a regular constant.
uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
switch (Opc) {
default: llvm_unreachable("Unknown target vector shift node");
case X86ISD::VSHLI:
case X86ISD::VSRLI:
case X86ISD::VSRAI:
return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
return DAG.getNode(Opc, dl, VT, SrcOp,
DAG.getConstant(ShiftAmt, MVT::i32));
}
}

9
test/CodeGen/X86/2012-07-15-tconst_shl.ll Normal file
View File

@ -0,0 +1,9 @@
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+avx2
; make sure that we are not crashing.
define <16 x i32> @autogen_SD34717() {
BB:
%Shuff7 = shufflevector <16 x i32> zeroinitializer, <16 x i32> zeroinitializer, <16 x i32> <i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 24, i32 26, i32 28, i32 30, i32 undef>
%B9 = lshr <16 x i32> zeroinitializer, %Shuff7
ret <16 x i32> %B9
}