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[AArch64]: BFloat MatMul Intrinsics&CodeGen
This patch upstreams support for BFloat Matrix Multiplication Intrinsics and Code Generation from __bf16 to AArch64. This includes IR intrinsics. Unittests are provided as needed. AArch32 Intrinsics + CodeGen will come after this patch. This patch is part of a series implementing the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile The following people contributed to this patch: Luke Geeson - Momchil Velikov - Mikhail Maltsev - Luke Cheeseman Reviewers: SjoerdMeijer, t.p.northover, sdesmalen, labrinea, miyuki, stuij Reviewed By: miyuki, stuij Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits, llvm-commits, miyuki, chill, pbarrio, stuij Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D80752 Change-Id: I174f0fd0f600d04e3799b06a7da88973c6c0703f
This commit is contained in:
Luke Geeson
parent
15ca470585
commit
a099df1a66
@ -178,6 +178,12 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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class AdvSIMD_FML_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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}
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// Arithmetic ops
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@ -459,6 +465,11 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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def int_aarch64_neon_smmla : AdvSIMD_MatMul_Intrinsic;
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def int_aarch64_neon_usmmla : AdvSIMD_MatMul_Intrinsic;
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def int_aarch64_neon_usdot : AdvSIMD_Dot_Intrinsic;
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def int_aarch64_neon_bfdot : AdvSIMD_Dot_Intrinsic;
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def int_aarch64_neon_bfmmla : AdvSIMD_MatMul_Intrinsic;
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def int_aarch64_neon_bfmlalb : AdvSIMD_FML_Intrinsic;
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def int_aarch64_neon_bfmlalt : AdvSIMD_FML_Intrinsic;
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// v8.2-A FP16 Fused Multiply-Add Long
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def int_aarch64_neon_fmlal : AdvSIMD_FP16FML_Intrinsic;
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@ -7815,16 +7815,19 @@ let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in {
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class BaseSIMDThreeSameVectorBFDot<bit Q, bit U, string asm, string kind1,
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string kind2, RegisterOperand RegType,
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ValueType AccumType, ValueType InputType>
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: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, []> {
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: BaseSIMDThreeSameVectorTied<Q, U, 0b010, 0b11111, RegType, asm, kind1, [(set (AccumType RegType:$dst),
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(int_aarch64_neon_bfdot (AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType RegType:$Rm)))]> {
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let AsmString = !strconcat(asm,
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"{\t$Rd" # kind1 # ", $Rn" # kind2 #
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", $Rm" # kind2 # "}");
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}
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multiclass SIMDThreeSameVectorBFDot<bit U, string asm> {
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def v4f16 : BaseSIMDThreeSameVectorBFDot<0, U, asm, ".2s", ".4h", V64,
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def v4bf16 : BaseSIMDThreeSameVectorBFDot<0, U, asm, ".2s", ".4h", V64,
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v2f32, v8i8>;
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def v8f16 : BaseSIMDThreeSameVectorBFDot<1, U, asm, ".4s", ".8h", V128,
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def v8bf16 : BaseSIMDThreeSameVectorBFDot<1, U, asm, ".4s", ".8h", V128,
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v4f32, v16i8>;
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}
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@ -7837,7 +7840,13 @@ class BaseSIMDThreeSameVectorBF16DotI<bit Q, bit U, string asm,
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: BaseSIMDIndexedTied<Q, U, 0b0, 0b01, 0b1111,
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RegType, RegType, V128, VectorIndexS,
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asm, "", dst_kind, lhs_kind, rhs_kind,
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[]> {
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[(set (AccumType RegType:$dst),
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(AccumType (int_aarch64_neon_bfdot
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(AccumType RegType:$Rd),
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(InputType RegType:$Rn),
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(InputType (bitconvert (AccumType
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(AArch64duplane32 (v4f32 V128:$Rm),
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VectorIndexH:$idx)))))))]> {
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bits<2> idx;
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let Inst{21} = idx{0}; // L
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@ -7846,23 +7855,30 @@ class BaseSIMDThreeSameVectorBF16DotI<bit Q, bit U, string asm,
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multiclass SIMDThreeSameVectorBF16DotI<bit U, string asm> {
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def v4f16 : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
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def v4bf16 : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
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".2h", V64, v2f32, v8i8>;
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def v8f16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
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def v8bf16 : BaseSIMDThreeSameVectorBF16DotI<1, U, asm, ".4s", ".8h",
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".2h", V128, v4f32, v16i8>;
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}
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class SIMDBF16MLAL<bit Q, string asm>
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class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
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: BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
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[]> { // TODO: Add intrinsics
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[(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
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(v16i8 V128:$Rn),
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(v16i8 V128:$Rm)))]> {
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let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
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}
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class SIMDBF16MLALIndex<bit Q, string asm>
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class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
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: I<(outs V128:$dst),
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(ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
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"{\t$Rd.4s, $Rn.8h, $Rm.h$idx}", "$Rd = $dst",
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[]>, // TODO: Add intrinsics
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[(set (v4f32 V128:$dst),
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(v4f32 (OpNode (v4f32 V128:$Rd),
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(v16i8 V128:$Rn),
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(v16i8 (bitconvert (v8bf16
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(AArch64duplane16 (v8bf16 V128_lo:$Rm),
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VectorIndexH:$idx)))))))]>,
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Sched<[WriteV]> {
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bits<5> Rd;
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bits<5> Rn;
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@ -7884,7 +7900,10 @@ class SIMDBF16MLALIndex<bit Q, string asm>
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class SIMDThreeSameVectorBF16MatrixMul<string asm>
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: BaseSIMDThreeSameVectorTied<1, 1, 0b010, 0b11101,
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V128, asm, ".4s",
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[]> {
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[(set (v4f32 V128:$dst),
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(int_aarch64_neon_bfmmla (v4f32 V128:$Rd),
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(v16i8 V128:$Rn),
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(v16i8 V128:$Rm)))]> {
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let AsmString = !strconcat(asm, "{\t$Rd", ".4s", ", $Rn", ".8h",
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", $Rm", ".8h", "}");
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}
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@ -784,10 +784,10 @@ let Predicates = [HasBF16] in {
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defm BFDOT : SIMDThreeSameVectorBFDot<1, "bfdot">;
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defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">;
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def BFMMLA : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">;
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def BFMLALB : SIMDBF16MLAL<0, "bfmlalb">;
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def BFMLALT : SIMDBF16MLAL<1, "bfmlalt">;
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def BFMLALBIdx : SIMDBF16MLALIndex<0, "bfmlalb">;
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def BFMLALTIdx : SIMDBF16MLALIndex<1, "bfmlalt">;
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def BFMLALB : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>;
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def BFMLALT : SIMDBF16MLAL<1, "bfmlalt", int_aarch64_neon_bfmlalt>;
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def BFMLALBIdx : SIMDBF16MLALIndex<0, "bfmlalb", int_aarch64_neon_bfmlalb>;
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def BFMLALTIdx : SIMDBF16MLALIndex<1, "bfmlalt", int_aarch64_neon_bfmlalt>;
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def BFCVTN : SIMD_BFCVTN;
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def BFCVTN2 : SIMD_BFCVTN2;
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def BFCVT : BF16ToSinglePrecision<"bfcvt">;
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176
test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
Normal file
176
test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
Normal file
@ -0,0 +1,176 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple aarch64-arm-none-eabi -mattr=+bf16 %s -o - | FileCheck %s
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define <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfdot v0.2s, v1.4h, v2.4h
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <4 x bfloat> %a to <8 x i8>
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%1 = bitcast <4 x bfloat> %b to <8 x i8>
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%vbfdot1.i = tail call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %0, <8 x i8> %1)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfdot v0.4s, v1.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfdot1.i = tail call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfdot1.i
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}
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define <2 x float> @test_vbfdot_lane_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_lane_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK: bfdot v0.2s, v1.4h, v2.2h[0]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <4 x bfloat> %b to <2 x float>
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%shuffle = shufflevector <2 x float> %0, <2 x float> undef, <2 x i32> zeroinitializer
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%1 = bitcast <4 x bfloat> %a to <8 x i8>
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%2 = bitcast <2 x float> %shuffle to <8 x i8>
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%vbfdot1.i = tail call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %1, <8 x i8> %2)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_laneq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfdot v0.4s, v1.8h, v2.2h[3]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %b to <4 x float>
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%shuffle = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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%1 = bitcast <8 x bfloat> %a to <16 x i8>
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%2 = bitcast <4 x float> %shuffle to <16 x i8>
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%vbfdot1.i = tail call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %1, <16 x i8> %2)
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ret <4 x float> %vbfdot1.i
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}
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define <2 x float> @test_vbfdot_laneq_f32(<2 x float> %r, <4 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_laneq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfdot v0.2s, v1.4h, v2.2h[3]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %b to <4 x float>
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%shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 3, i32 3>
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%1 = bitcast <4 x bfloat> %a to <8 x i8>
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%2 = bitcast <2 x float> %shuffle to <8 x i8>
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%vbfdot1.i = tail call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %1, <8 x i8> %2)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_lane_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK: bfdot v0.4s, v1.8h, v2.2h[0]
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <4 x bfloat> %b to <2 x float>
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%shuffle = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> zeroinitializer
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%1 = bitcast <8 x bfloat> %a to <16 x i8>
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%2 = bitcast <4 x float> %shuffle to <16 x i8>
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%vbfdot1.i = tail call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %1, <16 x i8> %2)
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ret <4 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmmlaq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfmmla v0.4s, v1.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmmla1.i = tail call <4 x float> @llvm.aarch64.neon.bfmmla.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmmla1.i
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}
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define <4 x float> @test_vbfmlalbq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfmlalb v0.4s, v1.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmlalb1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlaltq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlaltq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfmlalt v0.4s, v1.8h, v2.8h
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; CHECK-NEXT: ret
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmlalt1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalt1.i
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}
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define <4 x float> @test_vbfmlalbq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_lane_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK: bfmlalb v0.4s, v1.8h, v2.h[0]
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; CHECK-NEXT: ret
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entry:
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%vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
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%vbfmlalb1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_laneq_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: bfmlalb v0.4s, v1.8h, v2.h[3]
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; CHECK-NEXT: ret
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entry:
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%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
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%vbfmlalb1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlaltq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlaltq_lane_f32:
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; CHECK: // %bb.0: // %entry
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; CHECK: bfmlalt v0.4s, v1.8h, v2.h[0]
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; CHECK-NEXT: ret
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entry:
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%vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer
|
||||
%0 = bitcast <8 x bfloat> %a to <16 x i8>
|
||||
%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
|
||||
%vbfmlalt1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
|
||||
ret <4 x float> %vbfmlalt1.i
|
||||
}
|
||||
|
||||
define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
|
||||
; CHECK-LABEL: test_vbfmlaltq_laneq_f32:
|
||||
; CHECK: // %bb.0: // %entry
|
||||
; CHECK-NEXT: bfmlalt v0.4s, v1.8h, v2.h[3]
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
|
||||
%0 = bitcast <8 x bfloat> %a to <16 x i8>
|
||||
%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
|
||||
%vbfmlalt1.i = tail call <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
|
||||
ret <4 x float> %vbfmlalt1.i
|
||||
}
|
||||
|
||||
declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float>, <8 x i8>, <8 x i8>) #2
|
||||
declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
|
||||
declare <4 x float> @llvm.aarch64.neon.bfmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
|
||||
declare <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
|
||||
declare <4 x float> @llvm.aarch64.neon.bfmlalt.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>) #2
|
||||
Loading…
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Reference in New Issue
Block a user