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Revert "[RISCV] Add GHC calling convention"
This reverts commit f8317bb256be2cd8ed81ebc567f0fa626b645f63 due to lack of proper attribution.
This commit is contained in:
Luís Marques
parent
74c7102943
commit
a0cb7fdce3
@ -325,11 +325,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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// to determine the end of the prologue.
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DebugLoc DL;
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// All calls are tail calls in GHC calling conv, and functions have no
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// prologue/epilogue.
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if (MF.getFunction().getCallingConv() == CallingConv::GHC)
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return;
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// Emit prologue for shadow call stack.
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emitSCSPrologue(MF, MBB, MBBI, DL);
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@ -505,11 +500,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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Register FPReg = getFPReg(STI);
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Register SPReg = getSPReg(STI);
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// All calls are tail calls in GHC calling conv, and functions have no
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// prologue/epilogue.
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if (MF.getFunction().getCallingConv() == CallingConv::GHC)
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return;
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// Get the insert location for the epilogue. If there were no terminators in
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// the block, get the last instruction.
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MachineBasicBlock::iterator MBBI = MBB.end();
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@ -665,10 +665,6 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
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TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
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if (DAG.getMachineFunction().getFunction().getCallingConv() ==
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CallingConv::GHC)
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report_fatal_error("In GHC calling convention TLS is not supported");
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SDValue Addr;
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switch (Model) {
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case TLSModel::LocalExec:
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@ -2244,71 +2240,22 @@ static bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
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return true; // CC didn't match.
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}
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static bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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if (LocVT == MVT::i32 || LocVT == MVT::i64) {
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// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
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// s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11
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static const MCPhysReg GPRList[] = {
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RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22,
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RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27};
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if (unsigned Reg = State.AllocateReg(GPRList)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return false;
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}
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}
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if (LocVT == MVT::f32) {
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// Pass in STG registers: F1, ..., F6
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// fs0 ... fs5
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static const MCPhysReg FPR32List[] = {RISCV::F8_F, RISCV::F9_F,
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RISCV::F18_F, RISCV::F19_F,
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RISCV::F20_F, RISCV::F21_F};
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if (unsigned Reg = State.AllocateReg(FPR32List)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return false;
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}
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}
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if (LocVT == MVT::f64) {
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// Pass in STG registers: D1, ..., D6
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// fs6 ... fs11
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static const MCPhysReg FPR64List[] = {RISCV::F22_D, RISCV::F23_D,
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RISCV::F24_D, RISCV::F25_D,
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RISCV::F26_D, RISCV::F27_D};
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if (unsigned Reg = State.AllocateReg(FPR64List)) {
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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return false;
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}
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}
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report_fatal_error("No registers left in GHC calling convention");
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return true;
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}
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// Transform physical registers into virtual registers.
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SDValue RISCVTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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switch (CallConv) {
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default:
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report_fatal_error("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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break;
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case CallingConv::GHC:
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if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] ||
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!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD])
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report_fatal_error(
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"GHC calling convention requires the F and D instruction set extensions");
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}
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MachineFunction &MF = DAG.getMachineFunction();
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const Function &Func = MF.getFunction();
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if (Func.hasFnAttribute("interrupt")) {
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if (!Func.arg_empty())
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@ -2335,8 +2282,6 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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if (CallConv == CallingConv::Fast)
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CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC);
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else if (CallConv == CallingConv::GHC)
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CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC);
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else
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analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
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@ -2537,8 +2482,6 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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if (CallConv == CallingConv::Fast)
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ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC);
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else if (CallConv == CallingConv::GHC)
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ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
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else
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analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
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@ -2826,9 +2769,6 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
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nullptr);
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if (CallConv == CallingConv::GHC && !RVLocs.empty())
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report_fatal_error("GHC functions return void only");
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SDValue Glue;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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@ -45,8 +45,6 @@ RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
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const MCPhysReg *
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RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
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if (MF->getFunction().getCallingConv() == CallingConv::GHC)
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return CSR_NoRegs_SaveList;
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if (MF->getFunction().hasFnAttribute("interrupt")) {
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if (Subtarget.hasStdExtD())
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return CSR_XLEN_F64_Interrupt_SaveList;
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@ -193,11 +191,9 @@ Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const uint32_t *
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RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
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CallingConv::ID CC) const {
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CallingConv::ID /*CC*/) const {
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auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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if (CC == CallingConv::GHC)
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return CSR_NoRegs_RegMask;
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switch (Subtarget.getTargetABI()) {
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default:
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llvm_unreachable("Unrecognized ABI");
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@ -1,114 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s
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; Check the GHC call convention works (rv32)
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@base = external global i32 ; assigned to register: s1
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@sp = external global i32 ; assigned to register: s2
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@hp = external global i32 ; assigned to register: s3
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@r1 = external global i32 ; assigned to register: s4
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@r2 = external global i32 ; assigned to register: s5
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@r3 = external global i32 ; assigned to register: s6
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@r4 = external global i32 ; assigned to register: s7
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@r5 = external global i32 ; assigned to register: s8
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@r6 = external global i32 ; assigned to register: s9
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@r7 = external global i32 ; assigned to register: s10
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@splim = external global i32 ; assigned to register: s11
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@f1 = external global float ; assigned to register: fs0
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@f2 = external global float ; assigned to register: fs1
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@f3 = external global float ; assigned to register: fs2
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@f4 = external global float ; assigned to register: fs3
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@f5 = external global float ; assigned to register: fs4
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@f6 = external global float ; assigned to register: fs5
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@d1 = external global double ; assigned to register: fs6
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@d2 = external global double ; assigned to register: fs7
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@d3 = external global double ; assigned to register: fs8
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@d4 = external global double ; assigned to register: fs9
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@d5 = external global double ; assigned to register: fs10
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@d6 = external global double ; assigned to register: fs11
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define ghccc void @foo() nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a0, %hi(d6)
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; CHECK-NEXT: fld fs11, %lo(d6)(a0)
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; CHECK-NEXT: lui a0, %hi(d5)
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; CHECK-NEXT: fld fs10, %lo(d5)(a0)
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; CHECK-NEXT: lui a0, %hi(d4)
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; CHECK-NEXT: fld fs9, %lo(d4)(a0)
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; CHECK-NEXT: lui a0, %hi(d3)
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; CHECK-NEXT: fld fs8, %lo(d3)(a0)
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; CHECK-NEXT: lui a0, %hi(d2)
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; CHECK-NEXT: fld fs7, %lo(d2)(a0)
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; CHECK-NEXT: lui a0, %hi(d1)
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; CHECK-NEXT: fld fs6, %lo(d1)(a0)
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; CHECK-NEXT: lui a0, %hi(f6)
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; CHECK-NEXT: flw fs5, %lo(f6)(a0)
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; CHECK-NEXT: lui a0, %hi(f5)
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; CHECK-NEXT: flw fs4, %lo(f5)(a0)
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; CHECK-NEXT: lui a0, %hi(f4)
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; CHECK-NEXT: flw fs3, %lo(f4)(a0)
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; CHECK-NEXT: lui a0, %hi(f3)
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; CHECK-NEXT: flw fs2, %lo(f3)(a0)
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; CHECK-NEXT: lui a0, %hi(f2)
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; CHECK-NEXT: flw fs1, %lo(f2)(a0)
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; CHECK-NEXT: lui a0, %hi(f1)
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; CHECK-NEXT: flw fs0, %lo(f1)(a0)
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; CHECK-NEXT: lui a0, %hi(splim)
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; CHECK-NEXT: lw s11, %lo(splim)(a0)
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; CHECK-NEXT: lui a0, %hi(r7)
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; CHECK-NEXT: lw s10, %lo(r7)(a0)
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; CHECK-NEXT: lui a0, %hi(r6)
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; CHECK-NEXT: lw s9, %lo(r6)(a0)
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; CHECK-NEXT: lui a0, %hi(r5)
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; CHECK-NEXT: lw s8, %lo(r5)(a0)
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; CHECK-NEXT: lui a0, %hi(r4)
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; CHECK-NEXT: lw s7, %lo(r4)(a0)
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; CHECK-NEXT: lui a0, %hi(r3)
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; CHECK-NEXT: lw s6, %lo(r3)(a0)
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; CHECK-NEXT: lui a0, %hi(r2)
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; CHECK-NEXT: lw s5, %lo(r2)(a0)
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; CHECK-NEXT: lui a0, %hi(r1)
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; CHECK-NEXT: lw s4, %lo(r1)(a0)
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; CHECK-NEXT: lui a0, %hi(hp)
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; CHECK-NEXT: lw s3, %lo(hp)(a0)
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; CHECK-NEXT: lui a0, %hi(sp)
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; CHECK-NEXT: lw s2, %lo(sp)(a0)
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; CHECK-NEXT: lui a0, %hi(base)
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; CHECK-NEXT: lw s1, %lo(base)(a0)
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; CHECK-NEXT: tail bar
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entry:
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%0 = load double, double* @d6
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%1 = load double, double* @d5
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%2 = load double, double* @d4
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%3 = load double, double* @d3
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%4 = load double, double* @d2
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%5 = load double, double* @d1
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%6 = load float, float* @f6
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%7 = load float, float* @f5
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%8 = load float, float* @f4
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%9 = load float, float* @f3
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%10 = load float, float* @f2
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%11 = load float, float* @f1
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%12 = load i32, i32* @splim
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%13 = load i32, i32* @r7
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%14 = load i32, i32* @r6
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%15 = load i32, i32* @r5
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%16 = load i32, i32* @r4
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%17 = load i32, i32* @r3
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%18 = load i32, i32* @r2
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%19 = load i32, i32* @r1
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%20 = load i32, i32* @hp
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%21 = load i32, i32* @sp
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%22 = load i32, i32* @base
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tail call ghccc void @bar(i32 %22, i32 %21, i32 %20, i32 %19, i32 %18, i32 %17, i32 %16, i32 %15, i32 %14, i32 %13, i32 %12,
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float %11, float %10, float %9, float %8, float %7, float %6,
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double %5, double %4, double %3, double %2, double %1, double %0) nounwind
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ret void
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}
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declare ghccc void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
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float, float, float, float, float, float,
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double, double, double, double, double, double)
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@ -1,114 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d < %s | FileCheck %s
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; Check the GHC call convention works (rv64)
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@base = external global i64 ; assigned to register: s1
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@sp = external global i64 ; assigned to register: s2
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@hp = external global i64 ; assigned to register: s3
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@r1 = external global i64 ; assigned to register: s4
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@r2 = external global i64 ; assigned to register: s5
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@r3 = external global i64 ; assigned to register: s6
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@r4 = external global i64 ; assigned to register: s7
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@r5 = external global i64 ; assigned to register: s8
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@r6 = external global i64 ; assigned to register: s9
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@r7 = external global i64 ; assigned to register: s10
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@splim = external global i64 ; assigned to register: s11
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@f1 = external global float ; assigned to register: fs0
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@f2 = external global float ; assigned to register: fs1
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@f3 = external global float ; assigned to register: fs2
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@f4 = external global float ; assigned to register: fs3
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@f5 = external global float ; assigned to register: fs4
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@f6 = external global float ; assigned to register: fs5
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@d1 = external global double ; assigned to register: fs6
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@d2 = external global double ; assigned to register: fs7
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@d3 = external global double ; assigned to register: fs8
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@d4 = external global double ; assigned to register: fs9
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@d5 = external global double ; assigned to register: fs10
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@d6 = external global double ; assigned to register: fs11
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define ghccc void @foo() nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a0, %hi(d6)
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; CHECK-NEXT: fld fs11, %lo(d6)(a0)
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; CHECK-NEXT: lui a0, %hi(d5)
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; CHECK-NEXT: fld fs10, %lo(d5)(a0)
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; CHECK-NEXT: lui a0, %hi(d4)
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; CHECK-NEXT: fld fs9, %lo(d4)(a0)
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; CHECK-NEXT: lui a0, %hi(d3)
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; CHECK-NEXT: fld fs8, %lo(d3)(a0)
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; CHECK-NEXT: lui a0, %hi(d2)
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; CHECK-NEXT: fld fs7, %lo(d2)(a0)
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; CHECK-NEXT: lui a0, %hi(d1)
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; CHECK-NEXT: fld fs6, %lo(d1)(a0)
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; CHECK-NEXT: lui a0, %hi(f6)
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; CHECK-NEXT: flw fs5, %lo(f6)(a0)
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; CHECK-NEXT: lui a0, %hi(f5)
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; CHECK-NEXT: flw fs4, %lo(f5)(a0)
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; CHECK-NEXT: lui a0, %hi(f4)
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; CHECK-NEXT: flw fs3, %lo(f4)(a0)
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; CHECK-NEXT: lui a0, %hi(f3)
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; CHECK-NEXT: flw fs2, %lo(f3)(a0)
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; CHECK-NEXT: lui a0, %hi(f2)
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; CHECK-NEXT: flw fs1, %lo(f2)(a0)
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; CHECK-NEXT: lui a0, %hi(f1)
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; CHECK-NEXT: flw fs0, %lo(f1)(a0)
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; CHECK-NEXT: lui a0, %hi(splim)
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; CHECK-NEXT: ld s11, %lo(splim)(a0)
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; CHECK-NEXT: lui a0, %hi(r7)
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; CHECK-NEXT: ld s10, %lo(r7)(a0)
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; CHECK-NEXT: lui a0, %hi(r6)
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; CHECK-NEXT: ld s9, %lo(r6)(a0)
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; CHECK-NEXT: lui a0, %hi(r5)
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; CHECK-NEXT: ld s8, %lo(r5)(a0)
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; CHECK-NEXT: lui a0, %hi(r4)
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; CHECK-NEXT: ld s7, %lo(r4)(a0)
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; CHECK-NEXT: lui a0, %hi(r3)
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; CHECK-NEXT: ld s6, %lo(r3)(a0)
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; CHECK-NEXT: lui a0, %hi(r2)
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; CHECK-NEXT: ld s5, %lo(r2)(a0)
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; CHECK-NEXT: lui a0, %hi(r1)
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; CHECK-NEXT: ld s4, %lo(r1)(a0)
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; CHECK-NEXT: lui a0, %hi(hp)
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; CHECK-NEXT: ld s3, %lo(hp)(a0)
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; CHECK-NEXT: lui a0, %hi(sp)
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; CHECK-NEXT: ld s2, %lo(sp)(a0)
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; CHECK-NEXT: lui a0, %hi(base)
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; CHECK-NEXT: ld s1, %lo(base)(a0)
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; CHECK-NEXT: tail bar
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entry:
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%0 = load double, double* @d6
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%1 = load double, double* @d5
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%2 = load double, double* @d4
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%3 = load double, double* @d3
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%4 = load double, double* @d2
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%5 = load double, double* @d1
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%6 = load float, float* @f6
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%7 = load float, float* @f5
|
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%8 = load float, float* @f4
|
||||
%9 = load float, float* @f3
|
||||
%10 = load float, float* @f2
|
||||
%11 = load float, float* @f1
|
||||
%12 = load i64, i64* @splim
|
||||
%13 = load i64, i64* @r7
|
||||
%14 = load i64, i64* @r6
|
||||
%15 = load i64, i64* @r5
|
||||
%16 = load i64, i64* @r4
|
||||
%17 = load i64, i64* @r3
|
||||
%18 = load i64, i64* @r2
|
||||
%19 = load i64, i64* @r1
|
||||
%20 = load i64, i64* @hp
|
||||
%21 = load i64, i64* @sp
|
||||
%22 = load i64, i64* @base
|
||||
tail call ghccc void @bar(i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
|
||||
float %11, float %10, float %9, float %8, float %7, float %6,
|
||||
double %5, double %4, double %3, double %2, double %1, double %0) nounwind
|
||||
ret void
|
||||
}
|
||||
|
||||
declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
|
||||
float, float, float, float, float, float,
|
||||
double, double, double, double, double, double)
|
||||
Loading…
Reference in New Issue
Block a user