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Add a pattern for a nvcast from v2f64 -> v4f32

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Since the NvCast is generated by the selection process the concerns about
endianess and bit reversal don't apply.

rdar://21703486

llvm-svn: 241611
This commit is contained in:
Arnold Schwaighofer 2015-07-07 18:31:55 +00:00
parent 19bede10ac
commit a112326960
2 changed files with 9 additions and 0 deletions
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1
lib/Target/AArch64/AArch64InstrInfo.td
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@ -5315,6 +5315,7 @@ def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
let Predicates = [IsLE] in {
def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;

8
test/CodeGen/AArch64/arm64-nvcast.ll Normal file
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@ -0,0 +1,8 @@
; RUN: llc < %s -mtriple=arm64-apple-ios
define void @test(float * %p1, i32 %v1) {
entry:
%v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1
store float %v2, float* %p1, align 4
ret void
}