mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
llvm-svn: 134024
This commit is contained in:
Evan Cheng
parent
4a169be530
commit
a115f77785
@ -1720,35 +1720,15 @@ TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \
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# All of these files depend on tblgen and the .td files.
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$(INCTMPFiles) : $(TBLGEN) $(TDFiles)
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$(TARGET:%=$(ObjDir)/%GenRegisterNames.inc.tmp): \
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$(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) register names with tblgen"
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$(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
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$(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) register descriptions with tblgen"
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$(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
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$(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) register information header with tblgen"
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$(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
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$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) register info implementation with tblgen"
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$(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
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$(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) instruction names with tblgen"
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$(Verb) $(TableGen) -gen-instr-enums -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenInstrInfo.inc.tmp): \
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$(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) instruction information with tblgen"
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$(Verb) $(TableGen) -gen-instr-desc -o $(call SYSPATH, $@) $<
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$(Verb) $(TableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
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$(TARGET:%=$(ObjDir)/%GenAsmWriter.inc.tmp): \
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$(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir
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@ -7,7 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the McOperandInfo and McInstrDesc classes, which
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// This file defines the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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@ -30,7 +30,8 @@
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// Defines symbolic names for the ARM instructions.
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//
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#include "ARMGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "ARMGenInstrInfo.inc"
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namespace llvm {
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@ -18,7 +18,6 @@
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#include "ARMHazardRecognizer.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMGenInstrInfo.inc"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/GlobalValue.h"
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@ -35,6 +34,10 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/ADT/STLExtras.h"
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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using namespace llvm;
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static cl::opt<bool>
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@ -14,7 +14,6 @@
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterInfo.inc -gen-register-info)
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tablegen(ARMGenInstrNames.inc -gen-instr-enums)
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tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
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tablegen(ARMGenInstrInfo.inc -gen-instr-info)
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tablegen(ARMGenCodeEmitter.inc -gen-emitter)
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tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
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@ -71,6 +71,7 @@
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/// { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), 0 }
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///
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/// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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using namespace llvm;
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@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen
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TARGET = ARM
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = ARMGenRegisterInfo.inc \
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ARMGenInstrNames.inc ARMGenInstrInfo.inc \
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BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
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ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
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ARMGenDAGISel.inc ARMGenSubtarget.inc \
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ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
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@ -13,7 +13,6 @@
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#include "Thumb1InstrInfo.h"
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#include "ARM.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -15,7 +15,6 @@
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#include "ARM.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -50,6 +50,7 @@ namespace llvm {
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// Defines symbolic names for the Alpha instructions.
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//
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#include "AlphaGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "AlphaGenInstrInfo.inc"
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#endif
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@ -14,12 +14,14 @@
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#include "Alpha.h"
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#include "AlphaInstrInfo.h"
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#include "AlphaMachineFunctionInfo.h"
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#include "AlphaGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_MC_DESC
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#include "AlphaGenInstrInfo.inc"
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using namespace llvm;
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AlphaInstrInfo::AlphaInstrInfo()
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS Alpha.td)
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tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
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tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
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tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
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tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
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tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
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tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
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tablegen(AlphaGenCallingConv.inc -gen-callingconv)
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@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen
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TARGET = Alpha
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = AlphaGenRegisterInfo.inc \
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AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
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BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
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AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
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AlphaGenCallingConv.inc AlphaGenSubtarget.inc
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@ -34,6 +34,7 @@ namespace llvm {
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#include "BlackfinGenRegisterInfo.inc"
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// Defines symbolic names for the Blackfin instructions.
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#include "BlackfinGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "BlackfinGenInstrInfo.inc"
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#endif
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@ -19,6 +19,8 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_MC_DESC
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#include "BlackfinGenInstrInfo.inc"
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using namespace llvm;
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS Blackfin.td)
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tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
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tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
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tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
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tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
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tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
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tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
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tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
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@ -12,8 +12,8 @@ LIBRARYNAME = LLVMBlackfinCodeGen
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TARGET = Blackfin
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
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BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
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BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
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BlackfinGenAsmWriter.inc \
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BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
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BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
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@ -1,10 +1,9 @@
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set(LLVM_TARGET_DEFINITIONS SPU.td)
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tablegen(SPUGenInstrNames.inc -gen-instr-enums)
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tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(SPUGenCodeEmitter.inc -gen-emitter)
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tablegen(SPUGenRegisterInfo.inc -gen-register-info)
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tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
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tablegen(SPUGenInstrInfo.inc -gen-instr-info)
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tablegen(SPUGenDAGISel.inc -gen-dag-isel)
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tablegen(SPUGenSubtarget.inc -gen-subtarget)
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tablegen(SPUGenCallingConv.inc -gen-callingconv)
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@ -10,9 +10,9 @@
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LEVEL = ../../..
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LIBRARYNAME = LLVMCellSPUCodeGen
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TARGET = SPU
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BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
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BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
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SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
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SPUGenInstrInfo.inc SPUGenDAGISel.inc \
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SPUGenDAGISel.inc \
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SPUGenSubtarget.inc SPUGenCallingConv.inc
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DIRS = TargetInfo
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@ -30,6 +30,7 @@ namespace llvm {
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// Defines symbolic names for the SPU instructions.
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//
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#include "SPUGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "SPUGenInstrInfo.inc"
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#endif /* LLVM_TARGET_IBMCELLSPU_H */
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@ -15,7 +15,6 @@
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#include "SPUInstrInfo.h"
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#include "SPUInstrBuilder.h"
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#include "SPUTargetMachine.h"
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#include "SPUGenInstrInfo.inc"
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#include "SPUHazardRecognizers.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Debug.h"
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@ -23,6 +22,9 @@
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/MC/MCContext.h"
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#define GET_INSTRINFO_MC_DESC
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#include "SPUGenInstrInfo.inc"
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using namespace llvm;
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namespace {
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS MBlaze.td)
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tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
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tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
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tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
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tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
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tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
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tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
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tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
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@ -27,6 +27,7 @@
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// #include "MBlazeGenDecoderTables.inc"
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// #include "MBlazeGenRegisterNames.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "MBlazeGenInstrInfo.inc"
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#include "MBlazeGenEDInfo.inc"
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@ -43,6 +43,7 @@ namespace llvm {
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#include "MBlazeGenRegisterInfo.inc"
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// Defines symbolic names for the MBlaze instructions.
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#include "MBlazeGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "MBlazeGenInstrInfo.inc"
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#endif
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@ -20,6 +20,8 @@
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#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_MC_DESC
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#include "MBlazeGenInstrInfo.inc"
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using namespace llvm;
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@ -11,8 +11,8 @@ LIBRARYNAME = LLVMMBlazeCodeGen
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TARGET = MBlaze
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
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MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
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BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \
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MBlazeGenAsmWriter.inc \
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MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
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MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
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MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS MSP430.td)
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tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
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tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
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tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
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tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
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tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
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tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
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tablegen(MSP430GenCallingConv.inc -gen-callingconv)
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@ -51,6 +51,7 @@ namespace llvm {
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#include "MSP430GenRegisterInfo.inc"
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// Defines symbolic names for the MSP430 instructions.
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#include "MSP430GenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "MSP430GenInstrInfo.inc"
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#endif
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@ -15,7 +15,6 @@
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#include "MSP430InstrInfo.h"
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#include "MSP430MachineFunctionInfo.h"
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#include "MSP430TargetMachine.h"
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#include "MSP430GenInstrInfo.inc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -23,6 +22,9 @@
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_MC_DESC
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#include "MSP430GenInstrInfo.inc"
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using namespace llvm;
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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@ -12,8 +12,8 @@ LIBRARYNAME = LLVMMSP430CodeGen
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TARGET = MSP430
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
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MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
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BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
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MSP430GenAsmWriter.inc \
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MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
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MSP430GenSubtarget.inc
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@ -1,8 +1,7 @@
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set(LLVM_TARGET_DEFINITIONS Mips.td)
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tablegen(MipsGenRegisterInfo.inc -gen-register-info)
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tablegen(MipsGenInstrNames.inc -gen-instr-enums)
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tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
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tablegen(MipsGenInstrInfo.inc -gen-instr-info)
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tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
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tablegen(MipsGenDAGISel.inc -gen-dag-isel)
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tablegen(MipsGenCallingConv.inc -gen-callingconv)
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@ -12,8 +12,8 @@ LIBRARYNAME = LLVMMipsCodeGen
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TARGET = Mips
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
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MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
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BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
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MipsGenAsmWriter.inc \
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MipsGenDAGISel.inc MipsGenCallingConv.inc \
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MipsGenSubtarget.inc
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@ -39,6 +39,7 @@ namespace llvm {
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#include "MipsGenRegisterInfo.inc"
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// Defines symbolic names for the Mips instructions.
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#include "MipsGenInstrNames.inc"
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#define GET_INSTRINFO_ENUM
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#include "MipsGenInstrInfo.inc"
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#endif
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@ -18,6 +18,8 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "MipsGenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
@ -3,8 +3,7 @@ set(LLVM_TARGET_DEFINITIONS PTX.td)
|
||||
tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(PTXGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(PTXGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(PTXGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(PTXGenSubtarget.inc -gen-subtarget)
|
||||
|
||||
|
||||
@ -16,7 +16,6 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
|
||||
PTXGenCallingConv.inc \
|
||||
PTXGenDAGISel.inc \
|
||||
PTXGenInstrInfo.inc \
|
||||
PTXGenInstrNames.inc \
|
||||
PTXGenRegisterInfo.inc \
|
||||
PTXGenSubtarget.inc
|
||||
|
||||
|
||||
@ -51,6 +51,7 @@ namespace llvm {
|
||||
#include "PTXGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the PTX instructions.
|
||||
#include "PTXGenInstrNames.inc"
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "PTXGenInstrInfo.inc"
|
||||
|
||||
#endif // PTX_H
|
||||
|
||||
@ -21,10 +21,11 @@
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "PTXGenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
|
||||
: TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
|
||||
RI(_TM, *this), TM(_TM) {}
|
||||
|
||||
@ -1,11 +1,10 @@
|
||||
set(LLVM_TARGET_DEFINITIONS PPC.td)
|
||||
|
||||
tablegen(PPCGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(PPCGenCodeEmitter.inc -gen-emitter)
|
||||
tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
|
||||
tablegen(PPCGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(PPCGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(PPCGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(PPCGenCallingConv.inc -gen-callingconv)
|
||||
tablegen(PPCGenSubtarget.inc -gen-subtarget)
|
||||
|
||||
@ -12,7 +12,7 @@ LIBRARYNAME = LLVMPowerPCCodeGen
|
||||
TARGET = PPC
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
|
||||
BUILT_SOURCES = PPCGenRegisterInfo.inc \
|
||||
PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
|
||||
PPCGenInstrInfo.inc PPCGenDAGISel.inc \
|
||||
PPCGenSubtarget.inc PPCGenCallingConv.inc \
|
||||
|
||||
@ -89,6 +89,7 @@ namespace llvm {
|
||||
|
||||
// Defines symbolic names for the PowerPC instructions.
|
||||
//
|
||||
#include "PPCGenInstrNames.inc"
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "PPCGenInstrInfo.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
#include "PPCInstrBuilder.h"
|
||||
#include "PPCMachineFunctionInfo.h"
|
||||
#include "PPCPredicates.h"
|
||||
#include "PPCGenInstrInfo.inc"
|
||||
#include "PPCTargetMachine.h"
|
||||
#include "PPCHazardRecognizers.h"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
@ -29,6 +28,9 @@
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "PPCGenInstrInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
|
||||
extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
set(LLVM_TARGET_DEFINITIONS Sparc.td)
|
||||
|
||||
tablegen(SparcGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SparcGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(SparcGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(SparcGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(SparcGenSubtarget.inc -gen-subtarget)
|
||||
|
||||
@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSparcCodeGen
|
||||
TARGET = Sparc
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
|
||||
SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
|
||||
BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
|
||||
SparcGenAsmWriter.inc \
|
||||
SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
|
||||
|
||||
DIRS = TargetInfo
|
||||
|
||||
@ -41,7 +41,8 @@ namespace llvm {
|
||||
|
||||
// Defines symbolic names for the Sparc instructions.
|
||||
//
|
||||
#include "SparcGenInstrNames.inc"
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "SparcGenInstrInfo.inc"
|
||||
|
||||
|
||||
namespace llvm {
|
||||
|
||||
@ -19,8 +19,11 @@
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "SparcGenInstrInfo.inc"
|
||||
#include "SparcMachineFunctionInfo.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "SparcGenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
|
||||
|
||||
tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(SystemZGenCallingConv.inc -gen-callingconv)
|
||||
|
||||
@ -12,8 +12,8 @@ LIBRARYNAME = LLVMSystemZCodeGen
|
||||
TARGET = SystemZ
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
|
||||
SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
|
||||
BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
|
||||
SystemZGenAsmWriter.inc \
|
||||
SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
|
||||
|
||||
DIRS = TargetInfo
|
||||
|
||||
@ -57,6 +57,7 @@ namespace llvm {
|
||||
#include "SystemZGenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the SystemZ instructions.
|
||||
#include "SystemZGenInstrNames.inc"
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "SystemZGenInstrInfo.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -16,13 +16,16 @@
|
||||
#include "SystemZInstrInfo.h"
|
||||
#include "SystemZMachineFunctionInfo.h"
|
||||
#include "SystemZTargetMachine.h"
|
||||
#include "SystemZGenInstrInfo.inc"
|
||||
#include "llvm/Function.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/PseudoSourceValue.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "SystemZGenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
|
||||
|
||||
@ -2,8 +2,7 @@ set(LLVM_TARGET_DEFINITIONS X86.td)
|
||||
|
||||
tablegen(X86GenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
||||
tablegen(X86GenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(X86GenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(X86GenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(X86GenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
||||
tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
|
||||
|
||||
@ -16,19 +16,17 @@
|
||||
#include "X86ATTInstPrinter.h"
|
||||
#include "X86InstComments.h"
|
||||
#include "X86Subtarget.h"
|
||||
#include "MCTargetDesc/X86TargetDesc.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/Format.h"
|
||||
#include "llvm/Support/FormattedStream.h"
|
||||
#include "X86GenInstrNames.inc"
|
||||
#include <map>
|
||||
using namespace llvm;
|
||||
|
||||
// Include the auto-generated portion of the assembly writer.
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
#define GET_INSTRUCTION_NAME
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "X86GenAsmWriter.inc"
|
||||
|
||||
@ -13,7 +13,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86InstComments.h"
|
||||
#include "X86GenInstrNames.inc"
|
||||
#include "MCTargetDesc/X86TargetDesc.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "../Utils/X86ShuffleDecode.h"
|
||||
|
||||
@ -16,12 +16,12 @@
|
||||
#include "X86IntelInstPrinter.h"
|
||||
#include "X86InstComments.h"
|
||||
#include "X86Subtarget.h"
|
||||
#include "MCTargetDesc/X86TargetDesc.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/FormattedStream.h"
|
||||
#include "X86GenInstrNames.inc"
|
||||
#include <cctype>
|
||||
using namespace llvm;
|
||||
|
||||
|
||||
@ -12,11 +12,16 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86TargetDesc.h"
|
||||
#include "llvm/MC/MCInstrInfo.h"
|
||||
#include "llvm/MC/MCRegisterInfo.h"
|
||||
#include "llvm/Target/TargetRegistry.h"
|
||||
|
||||
#define GET_REGINFO_MC_DESC
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "X86GenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
MCRegisterInfo *createX86MCRegisterInfo() {
|
||||
|
||||
@ -26,4 +26,9 @@ extern Target TheX86_32Target, TheX86_64Target;
|
||||
#define GET_REGINFO_ENUM
|
||||
#include "X86GenRegisterInfo.inc"
|
||||
|
||||
// Defines symbolic names for the X86 instructions.
|
||||
//
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "X86GenInstrInfo.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -12,8 +12,7 @@ LIBRARYNAME = LLVMX86CodeGen
|
||||
TARGET = X86
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = X86GenRegisterInfo.inc \
|
||||
X86GenInstrNames.inc X86GenInstrInfo.inc \
|
||||
BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \
|
||||
X86GenAsmWriter.inc X86GenAsmMatcher.inc \
|
||||
X86GenAsmWriter1.inc X86GenDAGISel.inc \
|
||||
X86GenDisassemblerTables.inc X86GenFastISel.inc \
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
#ifndef TARGET_X86_H
|
||||
#define TARGET_X86_H
|
||||
|
||||
#include "MCTargetDesc/X86TargetDesc.h"
|
||||
#include "llvm/Support/DataTypes.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
|
||||
@ -86,10 +87,4 @@ MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
|
||||
|
||||
} // End llvm namespace
|
||||
|
||||
#include "MCTargetDesc/X86TargetDesc.h"
|
||||
|
||||
// Defines symbolic names for the X86 instructions.
|
||||
//
|
||||
#include "X86GenInstrNames.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -13,7 +13,6 @@
|
||||
|
||||
#include "X86InstrInfo.h"
|
||||
#include "X86.h"
|
||||
#include "X86GenInstrInfo.inc"
|
||||
#include "X86InstrBuilder.h"
|
||||
#include "X86MachineFunctionInfo.h"
|
||||
#include "X86Subtarget.h"
|
||||
@ -36,6 +35,9 @@
|
||||
#include "llvm/MC/MCAsmInfo.h"
|
||||
#include <limits>
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "X86GenInstrInfo.inc"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
static cl::opt<bool>
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
set(LLVM_TARGET_DEFINITIONS XCore.td)
|
||||
|
||||
tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
|
||||
tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
|
||||
tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
|
||||
tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
|
||||
tablegen(XCoreGenCallingConv.inc -gen-callingconv)
|
||||
|
||||
@ -12,8 +12,8 @@ LIBRARYNAME = LLVMXCoreCodeGen
|
||||
TARGET = XCore
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
|
||||
XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
|
||||
BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
|
||||
XCoreGenAsmWriter.inc \
|
||||
XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
|
||||
XCoreGenSubtarget.inc
|
||||
|
||||
|
||||
@ -37,6 +37,7 @@ namespace llvm {
|
||||
|
||||
// Defines symbolic names for the XCore instructions.
|
||||
//
|
||||
#include "XCoreGenInstrNames.inc"
|
||||
#define GET_INSTRINFO_ENUM
|
||||
#include "XCoreGenInstrInfo.inc"
|
||||
|
||||
#endif
|
||||
|
||||
@ -18,11 +18,13 @@
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineLocation.h"
|
||||
#include "XCoreGenInstrInfo.inc"
|
||||
#include "llvm/ADT/STLExtras.h"
|
||||
#include "llvm/Support/Debug.h"
|
||||
#include "llvm/Support/ErrorHandling.h"
|
||||
|
||||
#define GET_INSTRINFO_MC_DESC
|
||||
#include "XCoreGenInstrInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
namespace XCore {
|
||||
|
||||
|
||||
@ -156,9 +156,15 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
|
||||
|
||||
// run - Emit the main instruction description records for the target...
|
||||
void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
emitEnums(OS);
|
||||
|
||||
GatherItinClasses();
|
||||
|
||||
EmitSourceFileHeader("Target Instruction Descriptors", OS);
|
||||
|
||||
OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
|
||||
OS << "#undef GET_INSTRINFO_MC_DESC\n";
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
CodeGenTarget &Target = CDP.getTargetInfo();
|
||||
@ -202,6 +208,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
OperandInfoIDs, OS);
|
||||
OS << "};\n";
|
||||
OS << "} // End llvm namespace \n";
|
||||
|
||||
OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
|
||||
}
|
||||
|
||||
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
@ -283,3 +291,38 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
|
||||
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
||||
}
|
||||
|
||||
// emitEnums - Print out enum values for all of the instructions.
|
||||
void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
|
||||
EmitSourceFileHeader("Target Instruction Enum Values", OS);
|
||||
|
||||
OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
|
||||
OS << "#undef GET_INSTRINFO_ENUM\n";
|
||||
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
CodeGenTarget Target(Records);
|
||||
|
||||
// We must emit the PHI opcode first...
|
||||
std::string Namespace = Target.getInstNamespace();
|
||||
|
||||
if (Namespace.empty()) {
|
||||
fprintf(stderr, "No instructions defined!\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
const std::vector<const CodeGenInstruction*> &NumberedInstructions =
|
||||
Target.getInstructionsByEnumValue();
|
||||
|
||||
OS << "namespace " << Namespace << " {\n";
|
||||
OS << " enum {\n";
|
||||
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
||||
OS << " " << NumberedInstructions[i]->TheDef->getName()
|
||||
<< "\t= " << i << ",\n";
|
||||
}
|
||||
OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
|
||||
OS << " };\n}\n";
|
||||
OS << "} // End llvm namespace \n";
|
||||
|
||||
OS << "#endif // GET_INSTRINFO_ENUM\n\n";
|
||||
}
|
||||
|
||||
@ -39,8 +39,9 @@ public:
|
||||
void run(raw_ostream &OS);
|
||||
|
||||
private:
|
||||
typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
|
||||
|
||||
void emitEnums(raw_ostream &OS);
|
||||
|
||||
typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
|
||||
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
Record *InstrInfo,
|
||||
std::map<std::vector<Record*>, unsigned> &EL,
|
||||
|
||||
@ -28,7 +28,6 @@
|
||||
#include "EDEmitter.h"
|
||||
#include "Error.h"
|
||||
#include "FastISelEmitter.h"
|
||||
#include "InstrEnumEmitter.h"
|
||||
#include "InstrInfoEmitter.h"
|
||||
#include "IntrinsicEmitter.h"
|
||||
#include "LLVMCConfigurationEmitter.h"
|
||||
@ -55,7 +54,9 @@ enum ActionType {
|
||||
PrintRecords,
|
||||
GenEmitter,
|
||||
GenRegisterInfo,
|
||||
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
|
||||
GenInstrInfo,
|
||||
GenAsmWriter,
|
||||
GenAsmMatcher,
|
||||
GenARMDecoder,
|
||||
GenDisassembler,
|
||||
GenCallingConv,
|
||||
@ -95,9 +96,7 @@ namespace {
|
||||
"Generate machine code emitter"),
|
||||
clEnumValN(GenRegisterInfo, "gen-register-info",
|
||||
"Generate registers and register classes info"),
|
||||
clEnumValN(GenInstrEnums, "gen-instr-enums",
|
||||
"Generate enum values for instructions"),
|
||||
clEnumValN(GenInstrs, "gen-instr-desc",
|
||||
clEnumValN(GenInstrInfo, "gen-instr-info",
|
||||
"Generate instruction descriptions"),
|
||||
clEnumValN(GenCallingConv, "gen-callingconv",
|
||||
"Generate calling convention descriptions"),
|
||||
@ -260,10 +259,7 @@ int main(int argc, char **argv) {
|
||||
case GenRegisterInfo:
|
||||
RegisterInfoEmitter(Records).run(Out.os());
|
||||
break;
|
||||
case GenInstrEnums:
|
||||
InstrEnumEmitter(Records).run(Out.os());
|
||||
break;
|
||||
case GenInstrs:
|
||||
case GenInstrInfo:
|
||||
InstrInfoEmitter(Records).run(Out.os());
|
||||
break;
|
||||
case GenCallingConv:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user