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[ARC][NFC] Remove trailing space

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This commit is contained in:
Jim Lin 2020-02-25 16:12:22 +08:00
parent 75aaaf95b6
commit a11e0eb481
3 changed files with 44 additions and 44 deletions
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48
lib/Target/ARC/ARCInstrFormats.td
View File

@ -127,16 +127,16 @@ class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===//
// All 32-bit ARC instructions have a 5-bit "major" opcode class designator
// in bits 27-31.
//
// in bits 27-31.
//
// Some general naming conventions:
// N - Delay Slot bit. ARC v2 branch instructions have an optional delay slot
// which is encoded with this bit. When set, a delay slot exists.
// cc - Condition code.
// SX - Signed X-bit immediate.
// UX - Unsigned X-bit immediate.
//
// [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
//
// [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
// standard 32 general purpose registers, and allows use of additional
// (extension) registers. This also encodes an instruction that uses
// a 32-bit Long Immediate (LImm), using 0x3e==62 as the field value.
@ -166,7 +166,7 @@ class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
list<dag> pattern> :
F32_BR<major, outs, ins, b16, asmstr, pattern> {
bits<21> S21; // 2-byte aligned 21-bit byte-offset.
bits<5> cc;
bits<5> cc;
let Inst{26-18} = S21{10-2};
let Inst{15-6} = S21{20-11};
let Inst{4-0} = cc;
@ -328,7 +328,7 @@ class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
}
// 2-register, signed 12-bit immediate Dual Operand instruction.
// This instruction uses B as the first 2 operands (i.e., add B, B, -128).
// This instruction uses B as the first 2 operands (i.e., add B, B, -128).
// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
// |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
@ -336,7 +336,7 @@ class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
InstARC<4, outs, ins, asmstr, pattern> {
bits<6> B;
bits<12> S12;
let Inst{31-27} = major;
let Inst{26-24} = B{2-0};
let Inst{23-22} = 0b10;
@ -547,14 +547,14 @@ class F16_COMPACT<bits<1> i, dag outs, dag ins,
let Inst{15-11} = 0b01000;
let Inst{7-5} = h{2-0};
let Inst{2} = i;
let Inst{1-0} = h{4-3};
let Inst{1-0} = h{4-3};
}
// Compact Load/Add/Sub.
class F16_LD_ADD_SUB<dag outs, dag ins, string asmstr> :
InstARC<2, outs, ins, asmstr, []> {
bits<3> b;
bits<3> b;
let Inst{15-11} = 0b01001;
let Inst{10-8} = b;
}
@ -575,10 +575,10 @@ class F16_LD_SUB<bit i, string asmstr> :
class F16_ADD :
F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6),
"add_s\t$r, $b, $u6"> {
bit r;
bits<6> u6;
let Inst{7} = r;
let Inst{6-4} = u6{5-3};
let Inst{3} = 1;
@ -610,7 +610,7 @@ class F16_LDI_u7 :
bits<3> b;
bits<7> u7;
let Inst{10-8} = b;
let Inst{7-4} = u7{6-3};
let Inst{3} = 1;
@ -623,7 +623,7 @@ class F16_JLI_EI<bit i, string asmstr> :
!strconcat(asmstr, "\t$u10"), []> {
bits<10> u10;
let Inst{15-11} = 0b01011;
let Inst{10} = i;
let Inst{9-0} = u10;
@ -635,9 +635,9 @@ class F16_LD_ADD_RR<bits<2> i, string asmstr> :
asmstr, []> {
bits<3> a;
bits<3> b;
bits<3> b;
bits<3> c;
let Inst{15-11} = 0b01100;
let Inst{10-8} = b;
let Inst{7-5} = c;
@ -648,7 +648,7 @@ class F16_LD_ADD_RR<bits<2> i, string asmstr> :
// Load/Add GP-Relative.
class F16_GP_LD_ADD<bits<2> i, dag ins, string asmstr> :
InstARC<2, (outs), ins, asmstr, []> {
let Inst{15-11} = 0b11001;
let Inst{10-9} = i;
}
@ -663,7 +663,7 @@ class F16_ADD_IMM<bits<2> i, string asmstr> :
bits<3> b;
bits<3> c;
bits<3> u3;
let Inst{15-11} = 0b01101;
let Inst{10-8} = b;
let Inst{7-5} = c;
@ -689,8 +689,8 @@ class F16_OP_HREG<bits<3> i, dag outs, dag ins, string asmstr> :
class F16_OP_HREG30<bits<3> i, dag outs, dag ins, string asmstr> :
F16_OP_HREG<i, outs, ins, asmstr> {
bits<5> LImmReg = 0b11110;
bits<5> LImmReg = 0b11110;
let Inst{7-5} = LImmReg{2-0};
let Inst{1-0} = LImmReg{4-3};
}
@ -784,7 +784,7 @@ class F16_SH_SUB_BIT<bits<3> i, string asmstr> :
bits<3> b;
bits<5> u5;
let Inst{15-11} = 0b10111;
let Inst{10-8} = b;
let Inst{7-5} = i;
@ -816,7 +816,7 @@ class F16_SP_OPS_u7_aligned<bits<3> i,
bits<3> b3;
bits<7> u7;
let fieldB = b3;
let fieldU = u7{6-2};
let u7{1-0} = 0b00;
@ -826,7 +826,7 @@ class F16_SP_OPS_bconst<bits<3> b, string asmop> :
F16_SP_OPS_u7_aligned<0b101,
(outs), (ins immU<7>:$u7),
!strconcat(asmop, "\t%sp, %sp, $u7")> {
let fieldB = b;
}
@ -834,14 +834,14 @@ class F16_SP_OPS_uconst<bits<3> i,
dag outs, dag ins, string asmop> :
F16_SP_OPS_u7_aligned<i, outs, ins,
!strconcat(asmop, "\t$b3")> {
let fieldU = 0b00001;
}
class F16_SP_OPS_buconst<bits<3> i, string asmop> :
F16_SP_OPS_u7_aligned<i, (outs), (ins),
!strconcat(asmop, "\t%blink")> {
let fieldB = 0x000;
let fieldU = 0b10001;
}

24
lib/Target/ARC/ARCInstrInfo.td
View File

@ -344,7 +344,7 @@ let isBranch = 1, isTerminator = 1 in {
// At worst, this expands into 2 4-byte instructions.
def BRcc_rr_p : PseudoInstARC<(outs),
(ins btarget:$T, GPR32:$B, GPR32:$C, ccond:$cc),
"pbr$cc\t$B, $C, $T",
"pbr$cc\t$B, $C, $T",
[(ARCbrcc bb:$T, i32:$B, i32:$C, imm32:$cc)]>
{ let Size = 8; }
@ -430,7 +430,7 @@ def LEAVE_S : F16_SP_OPS<0b110,
(outs), (ins immU<7>:$u7), "leave_s\t$u7"> {
bits<7> u7;
let fieldB = u7{6-4};
let fieldU{4-1} = u7{3-0};
let fieldU{0} = 0b0;
@ -440,7 +440,7 @@ def ENTER_S : F16_SP_OPS<0b111,
(outs), (ins immU<6>:$u6), "enter_s\t$u6"> {
bits<6> u6;
let fieldB{2} = 0;
let fieldB{1-0} = u6{5-4};
let fieldU{4-1} = u6{3-0};
@ -452,19 +452,19 @@ def ENTER_S : F16_SP_OPS<0b111,
//----------------------------------------------------------------------------
class COMPACT_MOV_S :
F16_COMPACT<0b0, (outs GPR32:$g), (ins GPR32:$h),
"mov_s\t$g, $h"> {
"mov_s\t$g, $h"> {
let DecoderMethod = "DecodeMoveHRegInstruction";
}
def COMPACT_MOV_S_limm : COMPACT_MOV_S {
bits<32> LImm;
bits<32> LImm;
let Inst{47-16} = LImm;
bits<5> LImmReg = 0b11110;
bits<5> LImmReg = 0b11110;
let Inst{7-5} = LImmReg{2-0};
let Inst{1-0} = LImmReg{4-3};
let Size = 6;
let Size = 6;
}
def COMPACT_MOV_S_hreg : COMPACT_MOV_S;
@ -548,9 +548,9 @@ def GP_ADD_S : F16_GP_LD_ADD<0b11, (ins immS<11>:$s),
//----------------------------------------------------------------------------
def PCL_LD : InstARC<2, (outs GPR32:$b), (ins immU<10>:$u10),
"ld_s\t$b, [%pcl, $u10]", []> {
bits<3> b;
bits<10> u10;
bits<3> b;
bits<10> u10;
let Inst{15-11} = 0b11010;
let Inst{10-8} = b;
@ -587,11 +587,11 @@ def BL_S :
InstARC<2, (outs), (ins btargetS13:$s13), "bl_s\t$s13", []> {
let Inst{15-11} = 0b11111;
bits<13> s13;
let Inst{10-0} = s13{12-2};
let s13{1-0} = 0b00;
let isCall = 1;
let isBarrier = 1;
}

16
lib/Target/ARC/ARCRegisterInfo.td
View File

@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Declarations that describe the ARC register file
// Declarations that describe the ARC register file
//===----------------------------------------------------------------------===//
class ARCReg<string n, list<string> altNames> : Register<n, altNames> {
@ -27,35 +27,35 @@ class Status<string n> : ARCReg<n, []> {
// Integer registers
def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
let CostPerUse=1 in {
def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
def R10 : Core<10, "%r10">, DwarfRegNum<[10]>;
def R10 : Core<10, "%r10">, DwarfRegNum<[10]>;
def R11 : Core<11, "%r11">, DwarfRegNum<[11]>;
}
def R12 : Core<12, "%r12">, DwarfRegNum<[12]>;
def R13 : Core<13, "%r13">, DwarfRegNum<[13]>;
def R13 : Core<13, "%r13">, DwarfRegNum<[13]>;
def R14 : Core<14, "%r14">, DwarfRegNum<[14]>;
def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
let CostPerUse=1 in {
def R16 : Core<16, "%r16">, DwarfRegNum<[16]>;
def R17 : Core<17, "%r17">, DwarfRegNum<[17]>;
def R18 : Core<18, "%r18">, DwarfRegNum<[18]>;
def R18 : Core<18, "%r18">, DwarfRegNum<[18]>;
def R19 : Core<19, "%r19">, DwarfRegNum<[19]>;
def R20 : Core<20, "%r20">, DwarfRegNum<[20]>;
def R21 : Core<21, "%r21">, DwarfRegNum<[21]>;
def R21 : Core<21, "%r21">, DwarfRegNum<[21]>;
def R22 : Core<22, "%r22">, DwarfRegNum<[22]>;
def R23 : Core<23, "%r23">, DwarfRegNum<[23]>;
def R24 : Core<24, "%r24">, DwarfRegNum<[24]>;
def R25 : Core<25, "%r25">, DwarfRegNum<[25]>;
def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
def FP : Core<27, "%fp", ["%r27"]>, DwarfRegNum<[27]>;
def SP : Core<28, "%sp", ["%r28"]>, DwarfRegNum<[28]>;
def ILINK : Core<29, "%ilink">, DwarfRegNum<[29]>;