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[AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)

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Differential Revision: http://reviews.llvm.org/D22049

llvm-svn: 274852
This commit is contained in:
Valery Pykhtin 2016-07-08 15:12:46 +00:00
parent 1d87b206aa
commit a15c7e6b71
4 changed files with 24 additions and 4 deletions
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20
lib/Target/AMDGPU/SIInstrInfo.td
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@ -69,6 +69,11 @@ class sopk <bits<5> si, bits<5> vi = si> {
field bits<5> VI = vi;
}
class dsop <bits<8> si, bits<8> vi = si> {
field bits<8> SI = si;
field bits<8> VI = vi;
}
// Specify an SMRD opcode for SI and SMEM opcode for VI
// FIXME: This should really be bits<5> si, Tablegen crashes if
@ -2591,6 +2596,21 @@ class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm
let offset1 = offset{15-8};
}
multiclass DS_1A_RET_ <dsop op, string opName, RegisterClass rc,
dag outs = (outs rc:$vdst),
dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
string asm = opName#" $vdst, $addr"#"$offset$gds"> {
def "" : DS_Pseudo <opName, outs, ins, []>;
let data0 = 0, data1 = 0 in {
def _si : DS_Off16_Real_si <op.SI, opName, outs, ins, asm>;
def _vi : DS_Off16_Real_vi <op.VI, opName, outs, ins, asm>;
}
}
// TODO: DS_1A_RET can be inherited from DS_1A_RET_ but its not working
// for some reason. In fact we can remove this class if use dsop everywhere
multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
dag outs = (outs rc:$vdst),
dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),

2
lib/Target/AMDGPU/SIInstructions.td
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@ -825,7 +825,7 @@ defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32"
defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
let Uses = [EXEC], mayLoad =0, mayStore = 0, isConvergent = 1 in {
defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>;
defm DS_SWIZZLE_B32 : DS_1A_RET_ <dsop<0x35, 0x3d>, "ds_swizzle_b32", VGPR_32>;
}
let mayStore = 0 in {

2
test/MC/AMDGPU/ds.s
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@ -240,7 +240,7 @@ ds_max_rtn_f32 v8, v2, v4, v6
ds_swizzle_b32 v8, v2
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
ds_read_b32 v8, v2
// SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]

4
test/MC/Disassembler/AMDGPU/ds_vi.txt
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@ -162,8 +162,8 @@
# VI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
0x00 0x00 0x66 0xd8 0x02 0x04 0x06 0x08
# VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x6a 0xd8 0x02 0x00 0x00 0x08
# VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08