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https://github.com/RPCS3/llvm-mirror.git
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[X86] Use VT::changeVectorElementType helper where possible. NFCI.
This commit is contained in:
Simon Pilgrim
parent
c468872427
commit
a18c56e6ee
@ -2214,8 +2214,6 @@ EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
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return MVT::i8;
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if (Subtarget.hasAVX512()) {
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const unsigned NumElts = VT.getVectorNumElements();
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// Figure out what this type will be legalized to.
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EVT LegalVT = VT;
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while (getTypeAction(Context, LegalVT) != TypeLegal)
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@ -2223,7 +2221,7 @@ EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
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// If we got a 512-bit vector then we'll definitely have a vXi1 compare.
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if (LegalVT.getSimpleVT().is512BitVector())
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return EVT::getVectorVT(Context, MVT::i1, NumElts);
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return VT.changeVectorElementType(MVT::i1);
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if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
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// If we legalized to less than a 512-bit vector, then we will use a vXi1
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@ -2231,7 +2229,7 @@ EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
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// vXi16/vXi8.
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MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
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if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
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return EVT::getVectorVT(Context, MVT::i1, NumElts);
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return VT.changeVectorElementType(MVT::i1);
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}
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}
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@ -5847,9 +5845,9 @@ static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
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const SDLoc &dl, unsigned vectorWidth) {
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EVT VT = Vec.getValueType();
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EVT ElVT = VT.getVectorElementType();
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unsigned Factor = VT.getSizeInBits()/vectorWidth;
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unsigned Factor = VT.getSizeInBits() / vectorWidth;
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EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
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VT.getVectorNumElements()/Factor);
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VT.getVectorNumElements() / Factor);
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// Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
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unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
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@ -10388,7 +10386,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// it to i32 first.
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if (EltVT == MVT::i16 || EltVT == MVT::i8) {
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Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
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MVT ShufVT = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
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MVT ShufVT = MVT::getVectorVT(MVT::i32, VT.getSizeInBits() / 32);
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShufVT, Item);
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Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
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return DAG.getBitcast(VT, Item);
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@ -10471,7 +10469,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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SDValue NewBV = DAG.getBitcast(MVT::getVectorVT(WideEltVT, 2),
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DAG.getBuildVector(NarrowVT, dl, Ops));
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// Broadcast from v2i64/v2f64 and cast to final VT.
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MVT BcastVT = MVT::getVectorVT(WideEltVT, NumElems/2);
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MVT BcastVT = MVT::getVectorVT(WideEltVT, NumElems / 2);
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return DAG.getBitcast(VT, DAG.getNode(X86ISD::VBROADCAST, dl, BcastVT,
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NewBV));
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}
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@ -10480,7 +10478,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// For AVX-length vectors, build the individual 128-bit pieces and use
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// shuffles to put them in place.
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if (VT.getSizeInBits() > 128) {
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MVT HVT = MVT::getVectorVT(EltVT, NumElems/2);
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MVT HVT = MVT::getVectorVT(EltVT, NumElems / 2);
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// Build both the lower and upper subvector.
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SDValue Lower =
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@ -41437,8 +41435,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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if ((SelectableLHS && ZeroRHS) || (SelectableRHS && ZeroLHS)) {
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EVT SrcVT = SelectableLHS ? LHS.getOperand(0).getValueType()
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: RHS.getOperand(0).getValueType();
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unsigned NumSrcElts = SrcVT.getVectorNumElements();
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EVT SrcCondVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumSrcElts);
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EVT SrcCondVT = SrcVT.changeVectorElementType(MVT::i1);
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LHS = insertSubVector(DAG.getUNDEF(SrcVT), LHS, 0, DAG, DL,
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VT.getSizeInBits());
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RHS = insertSubVector(DAG.getUNDEF(SrcVT), RHS, 0, DAG, DL,
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@ -42551,7 +42548,7 @@ static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
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if ((NumElts % 2) != 0)
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return SDValue();
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EVT ReducedVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, NumElts);
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EVT ReducedVT = VT.changeVectorElementType(MVT::i16);
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// Shrink the operands of mul.
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SDValue NewN0 = DAG.getNode(ISD::TRUNCATE, DL, ReducedVT, N0);
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@ -44811,8 +44808,7 @@ static SDValue combineTruncateWithSat(SDValue In, EVT VT, const SDLoc &DL,
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// Only do this when the result is at least 64 bits or we'll leaving
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// dangling PACKSSDW nodes.
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if (SVT == MVT::i8 && InSVT == MVT::i32) {
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EVT MidVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16,
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VT.getVectorNumElements());
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EVT MidVT = VT.changeVectorElementType(MVT::i16);
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SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL,
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DAG, Subtarget);
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assert(Mid && "Failed to pack!");
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@ -45209,8 +45205,7 @@ reduceMaskedLoadToScalarLoad(MaskedLoadSDNode *ML, SelectionDAG &DAG,
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EVT CastVT = VT;
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if (EltVT == MVT::i64 && !Subtarget.is64Bit()) {
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EltVT = MVT::f64;
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CastVT =
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EVT::getVectorVT(*DAG.getContext(), EltVT, VT.getVectorNumElements());
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CastVT = VT.changeVectorElementType(EltVT);
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}
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SDValue Load =
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@ -45343,8 +45338,7 @@ static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS,
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EVT EltVT = VT.getVectorElementType();
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if (EltVT == MVT::i64 && !Subtarget.is64Bit()) {
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EltVT = MVT::f64;
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EVT CastVT =
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EVT::getVectorVT(*DAG.getContext(), EltVT, VT.getVectorNumElements());
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EVT CastVT = VT.changeVectorElementType(EltVT);
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Value = DAG.getBitcast(CastVT, Value);
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}
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SDValue Extract =
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@ -47428,7 +47422,7 @@ combineToExtendBoolVectorInReg(SDNode *N, SelectionDAG &DAG,
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Vec = DAG.getNode(ISD::AND, DL, VT, Vec, BitMask);
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// Compare against the bitmask and extend the result.
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EVT CCVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElts);
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EVT CCVT = VT.changeVectorElementType(MVT::i1);
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Vec = DAG.getSetCC(DL, CCVT, Vec, BitMask, ISD::SETEQ);
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Vec = DAG.getSExtOrTrunc(Vec, DL, VT);
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@ -48077,8 +48071,7 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG,
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if (auto *BV = dyn_cast<BuildVectorSDNode>(Index)) {
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if (BV->isConstant() && IndexWidth > 32 &&
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DAG.ComputeNumSignBits(Index) > (IndexWidth - 32)) {
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unsigned NumElts = Index.getValueType().getVectorNumElements();
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EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
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EVT NewVT = Index.getValueType().changeVectorElementType(MVT::i32);
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Index = DAG.getNode(ISD::TRUNCATE, DL, NewVT, Index);
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return rebuildGatherScatter(GorS, Index, Base, Scale, DAG);
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}
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@ -48092,8 +48085,7 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG,
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IndexWidth > 32 &&
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Index.getOperand(0).getScalarValueSizeInBits() <= 32 &&
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DAG.ComputeNumSignBits(Index) > (IndexWidth - 32)) {
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unsigned NumElts = Index.getValueType().getVectorNumElements();
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EVT NewVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
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EVT NewVT = Index.getValueType().changeVectorElementType(MVT::i32);
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Index = DAG.getNode(ISD::TRUNCATE, DL, NewVT, Index);
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return rebuildGatherScatter(GorS, Index, Base, Scale, DAG);
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}
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@ -48105,8 +48097,7 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG,
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// Make sure the index is either i32 or i64
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if (IndexWidth != 32 && IndexWidth != 64) {
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MVT EltVT = IndexWidth > 32 ? MVT::i64 : MVT::i32;
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EVT IndexVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
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Index.getValueType().getVectorNumElements());
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EVT IndexVT = Index.getValueType().changeVectorElementType(EltVT);
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Index = DAG.getSExtOrTrunc(Index, DL, IndexVT);
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return rebuildGatherScatter(GorS, Index, Base, Scale, DAG);
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}
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@ -48263,8 +48254,7 @@ static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG,
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// UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
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if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) {
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SDLoc dl(N);
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EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
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InVT.getVectorNumElements());
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EVT DstVT = InVT.changeVectorElementType(MVT::i32);
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SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
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// UINT_TO_FP isn't legal without AVX512 so use SINT_TO_FP.
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@ -48306,8 +48296,7 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
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// SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
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if (InVT.isVector() && InVT.getScalarSizeInBits() < 32) {
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SDLoc dl(N);
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EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
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InVT.getVectorNumElements());
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EVT DstVT = InVT.changeVectorElementType(MVT::i32);
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SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
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if (IsStrict)
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return DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {VT, MVT::Other},
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@ -48324,8 +48313,7 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
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if (NumSignBits >= (BitWidth - 31)) {
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EVT TruncVT = MVT::i32;
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if (InVT.isVector())
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TruncVT = EVT::getVectorVT(*DAG.getContext(), TruncVT,
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InVT.getVectorNumElements());
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TruncVT = InVT.changeVectorElementType(TruncVT);
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SDLoc dl(N);
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if (DCI.isBeforeLegalize() || TruncVT != MVT::v2i32) {
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Op0);
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@ -50074,8 +50062,7 @@ static SDValue combineEXTEND_VECTOR_INREG(SDNode *N, SelectionDAG &DAG,
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ISD::LoadExtType Ext = Opcode == ISD::SIGN_EXTEND_VECTOR_INREG
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? ISD::SEXTLOAD
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: ISD::ZEXTLOAD;
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EVT MemVT =
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EVT::getVectorVT(*DAG.getContext(), SVT, VT.getVectorNumElements());
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EVT MemVT = VT.changeVectorElementType(SVT);
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if (TLI.isLoadExtLegal(Ext, VT, MemVT)) {
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SDValue Load =
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DAG.getExtLoad(Ext, SDLoc(N), VT, Ld->getChain(), Ld->getBasePtr(),
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