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Fix for PR968: expand vector sdiv, udiv, srem, urem.
llvm-svn: 31220
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parent
7b6f145c8e
commit
a1ce4523e5
@ -287,7 +287,15 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
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setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
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@ -308,12 +316,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (Subtarget->hasSSE1()) {
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addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
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setOperationAction(ISD::AND, MVT::v4f32, Legal);
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setOperationAction(ISD::OR, MVT::v4f32, Legal);
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setOperationAction(ISD::XOR, MVT::v4f32, Legal);
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setOperationAction(ISD::ADD, MVT::v4f32, Legal);
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setOperationAction(ISD::SUB, MVT::v4f32, Legal);
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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setOperationAction(ISD::FADD, MVT::v4f32, Legal);
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setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
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setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
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setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
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setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
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@ -328,16 +334,17 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
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addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
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setOperationAction(ISD::ADD, MVT::v2f64, Legal);
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setOperationAction(ISD::ADD, MVT::v16i8, Legal);
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setOperationAction(ISD::ADD, MVT::v8i16, Legal);
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setOperationAction(ISD::ADD, MVT::v4i32, Legal);
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setOperationAction(ISD::SUB, MVT::v2f64, Legal);
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setOperationAction(ISD::SUB, MVT::v16i8, Legal);
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setOperationAction(ISD::SUB, MVT::v8i16, Legal);
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setOperationAction(ISD::SUB, MVT::v4i32, Legal);
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setOperationAction(ISD::MUL, MVT::v8i16, Legal);
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setOperationAction(ISD::MUL, MVT::v2f64, Legal);
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setOperationAction(ISD::FADD, MVT::v2f64, Legal);
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setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
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setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
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setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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