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Use SparseSet for the RAFast live virtual register map.
This makes RAFast 4% faster, and it gets rid of the dodgy DenseMap iteration. This also revealed that RAFast would sometimes dereference DenseMap iterators after erasing other elements from the map. That does seem to work in the current DenseMap implementation, but SparseSet doesn't allow it. llvm-svn: 151111
This commit is contained in:
Jakob Stoklund Olesen
parent
3b18c7d900
commit
a1db1a4669
@ -32,6 +32,7 @@
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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@ -68,16 +69,20 @@ namespace {
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// Everything we know about a live virtual register.
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struct LiveReg {
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MachineInstr *LastUse; // Last instr to use reg.
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unsigned VirtReg; // Virtual register number.
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unsigned PhysReg; // Currently held here.
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unsigned short LastOpNum; // OpNum on LastUse.
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bool Dirty; // Register needs spill.
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LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
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Dirty(false) {}
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explicit LiveReg(unsigned v)
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: LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
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unsigned getSparseSetKey() const {
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return TargetRegisterInfo::virtReg2Index(VirtReg);
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}
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};
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typedef DenseMap<unsigned, LiveReg> LiveRegMap;
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typedef LiveRegMap::value_type LiveRegEntry;
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typedef SparseSet<LiveReg> LiveRegMap;
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// LiveVirtRegs - This map contains entries for each virtual register
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// that is currently available in a physical register.
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@ -154,8 +159,16 @@ namespace {
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void usePhysReg(MachineOperand&);
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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unsigned calcSpillCost(unsigned PhysReg) const;
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void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
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void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
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void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
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LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
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return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
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}
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LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
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return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
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}
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LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
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LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator,
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unsigned Hint);
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LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint);
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LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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@ -218,10 +231,9 @@ void RAFast::addKillFlag(const LiveReg &LR) {
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/// killVirtReg - Mark virtreg as no longer available.
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void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
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addKillFlag(LRI->second);
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const LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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PhysRegState[LR.PhysReg] = regFree;
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addKillFlag(*LRI);
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assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg && "Broken RegState mapping");
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PhysRegState[LRI->PhysReg] = regFree;
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// Erase from LiveVirtRegs unless we're spilling in bulk.
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if (!isBulkSpilling)
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LiveVirtRegs.erase(LRI);
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@ -231,7 +243,7 @@ void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
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void RAFast::killVirtReg(unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"killVirtReg needs a virtual register");
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
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if (LRI != LiveVirtRegs.end())
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killVirtReg(LRI);
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}
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@ -241,7 +253,7 @@ void RAFast::killVirtReg(unsigned VirtReg) {
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
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LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
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assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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spillVirtReg(MI, LRI);
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}
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@ -249,18 +261,18 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
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/// spillVirtReg - Do the actual work of spilling.
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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LiveRegMap::iterator LRI) {
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LiveReg &LR = LRI->second;
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assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
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LiveReg &LR = *LRI;
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assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
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if (LR.Dirty) {
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// If this physreg is used by the instruction, we want to kill it on the
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// instruction, not on the spill.
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bool SpillKill = LR.LastUse != MI;
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LR.Dirty = false;
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DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI)
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DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
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<< " in " << PrintReg(LR.PhysReg, TRI));
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const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
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int FI = getStackSpaceFor(LRI->first, RC);
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const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
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int FI = getStackSpaceFor(LRI->VirtReg, RC);
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DEBUG(dbgs() << " to stack slot #" << FI << "\n");
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TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
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++NumStores; // Update statistics
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@ -268,7 +280,8 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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// If this register is used by DBG_VALUE then insert new DBG_VALUE to
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// identify spilled location as the place to find corresponding variable's
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// value.
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SmallVector<MachineInstr *, 4> &LRIDbgValues = LiveDbgValueMap[LRI->first];
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SmallVector<MachineInstr *, 4> &LRIDbgValues =
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LiveDbgValueMap[LRI->VirtReg];
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for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
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MachineInstr *DBG = LRIDbgValues[li];
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const MDNode *MDPtr =
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@ -431,8 +444,11 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
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DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
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<< PrintReg(PhysReg, TRI) << " is reserved already.\n");
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return spillImpossible;
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default:
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return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
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default: {
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LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
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assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
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return I->Dirty ? spillDirty : spillClean;
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}
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}
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// This is a disabled register, add up cost of aliases.
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@ -450,10 +466,13 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
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break;
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case regReserved:
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return spillImpossible;
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default:
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Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
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default: {
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LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
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assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
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Cost += I->Dirty ? spillDirty : spillClean;
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break;
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}
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}
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}
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return Cost;
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}
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@ -463,17 +482,27 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
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/// that PhysReg is the proper container for VirtReg now. The physical
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/// register must not be used for anything else when this is called.
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///
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void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
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DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to "
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void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) {
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DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
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<< PrintReg(PhysReg, TRI) << "\n");
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PhysRegState[PhysReg] = LRE.first;
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assert(!LRE.second.PhysReg && "Already assigned a physreg");
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LRE.second.PhysReg = PhysReg;
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PhysRegState[PhysReg] = LR.VirtReg;
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assert(!LR.PhysReg && "Already assigned a physreg");
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LR.PhysReg = PhysReg;
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}
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RAFast::LiveRegMap::iterator
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RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
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assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
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assignVirtToPhysReg(*LRI, PhysReg);
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return LRI;
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}
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/// allocVirtReg - Allocate a physical register for VirtReg.
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void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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const unsigned VirtReg = LRE.first;
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RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
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LiveRegMap::iterator LRI,
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unsigned Hint) {
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const unsigned VirtReg = LRI->VirtReg;
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Can only allocate virtual registers");
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@ -492,7 +521,9 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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if (Cost < spillDirty) {
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if (Cost)
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definePhysReg(MI, Hint, regFree);
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return assignVirtToPhysReg(LRE, Hint);
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// definePhysReg may kill virtual registers and modify LiveVirtRegs.
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// That invalidates LRI, so run a new lookup for VirtReg.
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return assignVirtToPhysReg(VirtReg, Hint);
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}
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}
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@ -501,8 +532,10 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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// First try to find a completely free register.
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for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
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unsigned PhysReg = *I;
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if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
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return assignVirtToPhysReg(LRE, PhysReg);
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if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) {
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assignVirtToPhysReg(*LRI, PhysReg);
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return LRI;
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}
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}
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DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
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@ -515,21 +548,25 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
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DEBUG(dbgs() << "\tCost: " << Cost << "\n");
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DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
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// Cost is 0 when all aliases are already disabled.
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if (Cost == 0)
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return assignVirtToPhysReg(LRE, *I);
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if (Cost == 0) {
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assignVirtToPhysReg(*LRI, *I);
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return LRI;
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}
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if (Cost < BestCost)
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BestReg = *I, BestCost = Cost;
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}
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if (BestReg) {
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definePhysReg(MI, BestReg, regFree);
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return assignVirtToPhysReg(LRE, BestReg);
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// definePhysReg may kill virtual registers and modify LiveVirtRegs.
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// That invalidates LRI, so run a new lookup for VirtReg.
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return assignVirtToPhysReg(VirtReg, BestReg);
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}
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// Nothing we can do. Report an error and keep going with a bad allocation.
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MI->emitError("ran out of registers during register allocation");
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definePhysReg(MI, *AO.begin(), regFree);
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assignVirtToPhysReg(LRE, *AO.begin());
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return assignVirtToPhysReg(VirtReg, *AO.begin());
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}
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/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
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@ -540,8 +577,7 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
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"Not a virtual register");
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LiveRegMap::iterator LRI;
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bool New;
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tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
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LiveReg &LR = LRI->second;
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tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
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if (New) {
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// If there is no hint, peek at the only use of this register.
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if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
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@ -551,18 +587,18 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
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if (UseMI.isCopyLike())
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Hint = UseMI.getOperand(0).getReg();
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}
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allocVirtReg(MI, *LRI, Hint);
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} else if (LR.LastUse) {
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LRI = allocVirtReg(MI, LRI, Hint);
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} else if (LRI->LastUse) {
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// Redefining a live register - kill at the last use, unless it is this
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// instruction defining VirtReg multiple times.
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if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
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addKillFlag(LR);
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if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
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addKillFlag(*LRI);
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}
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assert(LR.PhysReg && "Register not assigned");
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LR.LastUse = MI;
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LR.LastOpNum = OpNum;
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LR.Dirty = true;
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UsedInInstr.set(LR.PhysReg);
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assert(LRI->PhysReg && "Register not assigned");
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LRI->LastUse = MI;
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LRI->LastOpNum = OpNum;
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LRI->Dirty = true;
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UsedInInstr.set(LRI->PhysReg);
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return LRI;
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}
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@ -574,18 +610,17 @@ RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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"Not a virtual register");
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LiveRegMap::iterator LRI;
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bool New;
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tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
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LiveReg &LR = LRI->second;
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tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
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MachineOperand &MO = MI->getOperand(OpNum);
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if (New) {
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allocVirtReg(MI, *LRI, Hint);
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LRI = allocVirtReg(MI, LRI, Hint);
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
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<< PrintReg(LR.PhysReg, TRI) << "\n");
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TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
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<< PrintReg(LRI->PhysReg, TRI) << "\n");
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TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
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++NumLoads;
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} else if (LR.Dirty) {
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} else if (LRI->Dirty) {
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if (isLastUseOfLocalReg(MO)) {
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DEBUG(dbgs() << "Killing last use: " << MO << "\n");
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if (MO.isUse())
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@ -610,10 +645,10 @@ RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
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MO.setIsDead(false);
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}
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assert(LR.PhysReg && "Register not assigned");
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LR.LastUse = MI;
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LR.LastOpNum = OpNum;
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UsedInInstr.set(LR.PhysReg);
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assert(LRI->PhysReg && "Register not assigned");
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LRI->LastUse = MI;
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LRI->LastOpNum = OpNum;
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UsedInInstr.set(LRI->PhysReg);
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return LRI;
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}
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@ -690,7 +725,7 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
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<< DefIdx << ".\n");
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LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
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unsigned PhysReg = LRI->second.PhysReg;
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unsigned PhysReg = LRI->PhysReg;
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setPhysReg(MI, i, PhysReg);
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// Note: we don't update the def operand yet. That would cause the normal
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// def-scan to attempt spilling.
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@ -699,7 +734,7 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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// Reload the register, but don't assign to the operand just yet.
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// That would confuse the later phys-def processing pass.
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LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
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PartialDefs.push_back(LRI->second.PhysReg);
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PartialDefs.push_back(LRI->PhysReg);
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}
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}
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@ -713,7 +748,7 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
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continue;
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// Note: defineVirtReg may invalidate MO.
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LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
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unsigned PhysReg = LRI->second.PhysReg;
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unsigned PhysReg = LRI->PhysReg;
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if (setPhysReg(MI, i, PhysReg))
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VirtDead.push_back(Reg);
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}
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@ -794,7 +829,7 @@ void RAFast::AllocateBasicBlock() {
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DEBUG(dbgs() << "\nAllocating " << *MBB);
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PhysRegState.assign(TRI->getNumRegs(), regDisabled);
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assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
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assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
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MachineBasicBlock::iterator MII = MBB->begin();
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@ -822,25 +857,26 @@ void RAFast::AllocateBasicBlock() {
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case regReserved:
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dbgs() << "*";
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break;
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default:
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default: {
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dbgs() << '=' << PrintReg(PhysRegState[Reg]);
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if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
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LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
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assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
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if (I->Dirty)
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dbgs() << "*";
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assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
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"Bad inverse map");
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assert(I->PhysReg == Reg && "Bad inverse map");
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break;
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}
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}
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}
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dbgs() << '\n';
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// Check that LiveVirtRegs is the inverse.
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i) {
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assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
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assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
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"Bad map key");
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assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
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assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) &&
|
||||
"Bad map value");
|
||||
assert(PhysRegState[i->second.PhysReg] == i->first &&
|
||||
"Bad inverse map");
|
||||
assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
|
||||
}
|
||||
});
|
||||
|
||||
@ -854,9 +890,9 @@ void RAFast::AllocateBasicBlock() {
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
||||
LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
|
||||
LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
|
||||
if (LRI != LiveVirtRegs.end())
|
||||
setPhysReg(MI, i, LRI->second.PhysReg);
|
||||
setPhysReg(MI, i, LRI->PhysReg);
|
||||
else {
|
||||
int SS = StackSlotForVirtReg[Reg];
|
||||
if (SS == -1) {
|
||||
@ -971,7 +1007,7 @@ void RAFast::AllocateBasicBlock() {
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
|
||||
if (MO.isUse()) {
|
||||
LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
|
||||
unsigned PhysReg = LRI->second.PhysReg;
|
||||
unsigned PhysReg = LRI->PhysReg;
|
||||
CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
|
||||
if (setPhysReg(MI, i, PhysReg))
|
||||
killVirtReg(LRI);
|
||||
@ -1027,7 +1063,7 @@ void RAFast::AllocateBasicBlock() {
|
||||
continue;
|
||||
}
|
||||
LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
|
||||
unsigned PhysReg = LRI->second.PhysReg;
|
||||
unsigned PhysReg = LRI->PhysReg;
|
||||
if (setPhysReg(MI, i, PhysReg)) {
|
||||
VirtDead.push_back(Reg);
|
||||
CopyDst = 0; // cancel coalescing;
|
||||
@ -1089,6 +1125,7 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
|
||||
// initialize the virtual->physical register map to have a 'null'
|
||||
// mapping for all virtual registers
|
||||
StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
|
||||
LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
|
||||
|
||||
// Loop over all of the basic blocks, eliminating virtual register references
|
||||
for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user