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[AArch64] Check the expansion of BITREVERSE in regression test
Something I missed from Hal's review, rightly pointed out by Ben Kramer - we should make sure the expansion is properly checked as it can be easy for bugs to creep in. I've checked the scalar i8 expansion here and the vector i8 expansion in a previous commit. llvm-svn: 253024
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@ -14,10 +14,29 @@ define <2 x i16> @f(<2 x i16> %a) {
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declare i8 @llvm.bitreverse.i8(i8) readnone
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; Unfortunately some of the shift-and-inserts become BFIs, and some do not :(
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define i8 @g(i8 %a) {
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; CHECK-LABEL: g:
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; CHECK: lsl
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; CHECK: and
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; CHECK-DAG: lsr [[S5:w.*]], w0, #5
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; CHECK-DAG: lsr [[S4:w.*]], w0, #4
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; CHECK-DAG: lsr [[S3:w.*]], w0, #3
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; CHECK-DAG: lsr [[S2:w.*]], w0, #2
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; CHECK-DAG: lsl [[L1:w.*]], w0, #29
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; CHECK-DAG: lsl [[L2:w.*]], w0, #19
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; CHECK-DAG: lsl [[L3:w.*]], w0, #17
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; CHECK-DAG: and [[T1:w.*]], [[L1]], #0x40000000
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; CHECK-DAG: bfi [[T1]], w0, #31, #1
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; CHECK-DAG: bfi [[T1]], [[S2]], #29, #1
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; CHECK-DAG: bfi [[T1]], [[S3]], #28, #1
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; CHECK-DAG: bfi [[T1]], [[S4]], #27, #1
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; CHECK-DAG: bfi [[T1]], [[S5]], #26, #1
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; CHECK-DAG: and [[T2:w.*]], [[L2]], #0x2000000
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; CHECK-DAG: and [[T3:w.*]], [[L3]], #0x1000000
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; CHECK-DAG: orr [[T4:w.*]], [[T1]], [[T2]]
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; CHECK-DAG: orr [[T5:w.*]], [[T4]], [[T3]]
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; CHECK: lsr w0, [[T5]], #24
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%b = call i8 @llvm.bitreverse.i8(i8 %a)
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ret i8 %b
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}
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